From 436765010f266a2afd6c9afd15233225448a3e8d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 27 May 2020 21:23:32 +0100 Subject: [PATCH] ARM: dts: r8a7742-iwg21d-q7: Enable SGTL5000 audio codec This patch enables SGTL5000 audio codec on the carrier board. Signed-off-by: Lad Prabhakar Reviewed-by: Marian-Cristian Rotariu Link: https://lore.kernel.org/r/1590611013-26029-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm/boot/dts/r8a7742-iwg21d-q7.dts | 37 +++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts index f23c2ba..ff4fca9 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts @@ -23,6 +23,20 @@ stdout-path = "serial2:115200n8"; }; + audio_clock: audio_clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + }; + + reg_1p5v: 1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + vcc_sdhi2: regulator-vcc-sdhi2 { compatible = "regulator-fixed"; @@ -61,12 +75,35 @@ }; }; +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + reg = <0x0a>; + clocks = <&audio_clock>; + VDDA-supply = <®_3p3v>; + VDDIO-supply = <®_3p3v>; + VDDD-supply = <®_1p5v>; + }; +}; + &pfc { avb_pins: avb { groups = "avb_mdio", "avb_gmii"; function = "avb"; }; + i2c2_pins: i2c2 { + groups = "i2c2_b"; + function = "i2c2"; + }; + scifa2_pins: scifa2 { groups = "scifa2_data_c"; function = "scifa2"; -- 2.7.4