From 42d84fc1403e388fda83ce83f7897b4563d21c3f Mon Sep 17 00:00:00 2001 From: Andrew Jackson Date: Fri, 3 Oct 2014 09:29:01 +0100 Subject: [PATCH] ASoC: dwc: Ensure FIFOs are flushed to prevent channel swap If the FIFOs aren't flushed, the left/right channels may be swapped: this may occur if the FIFOs are not empty when the streams start. Signed-off-by: Andrew Jackson --- sound/soc/dwc/designware_i2s.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/sound/soc/dwc/designware_i2s.c b/sound/soc/dwc/designware_i2s.c index 605cd2a..42b7f8c 100644 --- a/sound/soc/dwc/designware_i2s.c +++ b/sound/soc/dwc/designware_i2s.c @@ -259,6 +259,7 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, */ do { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { + i2s_write_reg(dev->i2s_base, TXFFR, 1); i2s_write_reg(dev->i2s_base, TCR(ch_reg), xfer_resolution); i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02); @@ -266,6 +267,7 @@ static int dw_i2s_hw_params(struct snd_pcm_substream *substream, i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30); i2s_write_reg(dev->i2s_base, TER(ch_reg), 1); } else { + i2s_write_reg(dev->i2s_base, RXFFR, 1); i2s_write_reg(dev->i2s_base, RCR(ch_reg), xfer_resolution); i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07); -- 2.7.4