From 429749e23bd81edfcefca574647f65e45e903819 Mon Sep 17 00:00:00 2001 From: Uros Bizjak Date: Sun, 30 Mar 2014 19:38:57 +0200 Subject: [PATCH] sse.md (FMAMODE_NOVF512): New mode iterator. * config/i386/sse.md (FMAMODE_NOVF512): New mode iterator. (fma_fmadd_): Split out fma_fmadd_. Use FMAMODE_NOVF512 mode iterator. (fma_fmsub_): Ditto. (fma_fnmadd_): Ditto. (fma_fnmsub_): Ditto. (fma_fmaddsub_): Split out fma_fmaddsub_. Use VF_128_256 mode iterator. (fma_fmsubadd_): Ditto. From-SVN: r208948 --- gcc/ChangeLog | 49 +++++++----- gcc/config/i386/sse.md | 207 ++++++++++++++++++++++++++++++++++++------------- 2 files changed, 185 insertions(+), 71 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ded35eb..b7b6bca 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,20 @@ +2014-03-30 Uros Bizjak + + * config/i386/sse.md (FMAMODE_NOVF512): New mode iterator. + (fma_fmadd_): + Split out + fma_fmadd_. + Use FMAMODE_NOVF512 mode iterator. + (fma_fmsub_): Ditto. + (fma_fnmadd_): Ditto. + (fma_fnmsub_): Ditto. + (fma_fmaddsub_): + Split out + fma_fmaddsub_. + Use VF_128_256 mode iterator. + (fma_fmsubadd_): + Ditto. + 2014-03-28 Jan Hubicka * cgraph.c (cgraph_redirect_edge_call_stmt_to_callee): Clear @@ -67,7 +84,8 @@ 2014-03-28 Jan Hubicka * cgraph.c: Include expr.h and tree-dfa.h. - (cgraph_redirect_edge_call_stmt_to_callee): If call in noreturn; remove LHS. + (cgraph_redirect_edge_call_stmt_to_callee): If call in noreturn; + remove LHS. 2014-03-28 Vladimir Makarov @@ -111,8 +129,7 @@ Optimize vec_extract of 64-bit values, where the value being extracted is in the top word, where we can use scalar instructions. Add direct move and store support. Combine the big - endian/little endian vector select load support into a single - insn. + endian/little endian vector select load support into a single insn. (vsx_extract__internal1): Likewise. (vsx_extract__internal2): Likewise. (vsx_extract__load): Likewise. @@ -257,12 +274,13 @@ PR ipa/60315 * cif-code.def (UNREACHABLE) New code. - * ipa-inline.c (inline_small_functions): Skip edges to __builtlin_unreachable. + * ipa-inline.c (inline_small_functions): Skip edges to + __builtlin_unreachable. (estimate_edge_growth): Allow edges to __builtlin_unreachable. * ipa-inline-analysis.c (edge_set_predicate): Redirect edges with false predicate to __bulitin_unreachable. - (set_cond_stmt_execution_predicate): Fix issue when invert_tree_comparison - returns ERROR_MARK. + (set_cond_stmt_execution_predicate): Fix issue when + invert_tree_comparison returns ERROR_MARK. * ipa-pure-const.c (propagate_pure_const, propagate_nothrow): Do not propagate to inline clones. * cgraph.c (verify_edge_corresponds_to_fndecl): Allow redirection @@ -284,8 +302,8 @@ (addv4, subv4, mulv4): If operands[2] is CONST_INT, don't generate (sign_extend (const_int)). (*addv4, *subv4, *mulv4): Disallow CONST_INT_P - operands[2]. Use We constraint instead of and - predicate instead of . + operands[2]. Use We constraint instead of and + predicate instead of . (*addv4_1, *subv4_1, *mulv4_1): New insns. * config/i386/constraints.md (We): New constraint. * config/i386/predicates.md (x86_64_sext_operand, @@ -323,8 +341,7 @@ 2014-03-25 Richard Biener - * lto-wrapper.c (merge_and_complain): Handle OPT_fPIE like - OPT_fpie. + * lto-wrapper.c (merge_and_complain): Handle OPT_fPIE like OPT_fpie. (run_gcc): Likewise. 2014-03-25 Jakub Jelinek @@ -550,13 +567,10 @@ 2014-03-18 Basile Starynkevitch * plugin.def: Improve comment for PLUGIN_INCLUDE_FILE. - * doc/plugins.texi (Plugin callbacks): Mention - PLUGIN_INCLUDE_FILE. + * doc/plugins.texi (Plugin callbacks): Mention PLUGIN_INCLUDE_FILE. Italicize plugin event names in description. Explain that - PLUGIN_PRAGMAS has no sense for lto1. Explain - PLUGIN_INCLUDE_FILE. - Remind that no GCC functions should be called after - PLUGIN_FINISH. + PLUGIN_PRAGMAS has no sense for lto1. Explain PLUGIN_INCLUDE_FILE. + Remind that no GCC functions should be called after PLUGIN_FINISH. Explain what pragmas with expansion are. 2014-03-18 Martin Liska @@ -814,8 +828,7 @@ 2014-03-13 Cesar Philippidis - * lto-wrapper.c (maybe_unlink_file): Suppress diagnostic - messages. + * lto-wrapper.c (maybe_unlink_file): Suppress diagnostic messages. 2014-03-13 Jakub Jelinek diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index f30b27e..72a4d6d 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -2712,50 +2712,46 @@ (fma:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand") (match_operand:FMAMODEM 2 "nonimmediate_operand") - (match_operand:FMAMODEM 3 "nonimmediate_operand")))] - "") + (match_operand:FMAMODEM 3 "nonimmediate_operand")))]) (define_expand "fms4" [(set (match_operand:FMAMODEM 0 "register_operand") (fma:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand") (match_operand:FMAMODEM 2 "nonimmediate_operand") - (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))] - "") + (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))]) (define_expand "fnma4" [(set (match_operand:FMAMODEM 0 "register_operand") (fma:FMAMODEM (neg:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand")) (match_operand:FMAMODEM 2 "nonimmediate_operand") - (match_operand:FMAMODEM 3 "nonimmediate_operand")))] - "") + (match_operand:FMAMODEM 3 "nonimmediate_operand")))]) (define_expand "fnms4" [(set (match_operand:FMAMODEM 0 "register_operand") (fma:FMAMODEM (neg:FMAMODEM (match_operand:FMAMODEM 1 "nonimmediate_operand")) (match_operand:FMAMODEM 2 "nonimmediate_operand") - (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))] - "") + (neg:FMAMODEM (match_operand:FMAMODEM 3 "nonimmediate_operand"))))]) ;; The builtins for intrinsics are not constrained by SSE math enabled. -(define_mode_iterator FMAMODE [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") - (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") - (V4SF "TARGET_FMA || TARGET_FMA4") - (V2DF "TARGET_FMA || TARGET_FMA4") - (V8SF "TARGET_FMA || TARGET_FMA4") - (V4DF "TARGET_FMA || TARGET_FMA4") - (V16SF "TARGET_AVX512F") - (V8DF "TARGET_AVX512F")]) +(define_mode_iterator FMAMODE + [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (V4SF "TARGET_FMA || TARGET_FMA4") + (V2DF "TARGET_FMA || TARGET_FMA4") + (V8SF "TARGET_FMA || TARGET_FMA4") + (V4DF "TARGET_FMA || TARGET_FMA4") + (V16SF "TARGET_AVX512F") + (V8DF "TARGET_AVX512F")]) (define_expand "fma4i_fmadd_" [(set (match_operand:FMAMODE 0 "register_operand") (fma:FMAMODE (match_operand:FMAMODE 1 "nonimmediate_operand") (match_operand:FMAMODE 2 "nonimmediate_operand") - (match_operand:FMAMODE 3 "nonimmediate_operand")))] - "") + (match_operand:FMAMODE 3 "nonimmediate_operand")))]) (define_expand "avx512f_fmadd__maskz" [(match_operand:VF_512 0 "register_operand") @@ -2771,12 +2767,20 @@ DONE; }) +(define_mode_iterator FMAMODE_NOVF512 + [(SF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (DF "TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F") + (V4SF "TARGET_FMA || TARGET_FMA4") + (V2DF "TARGET_FMA || TARGET_FMA4") + (V8SF "TARGET_FMA || TARGET_FMA4") + (V4DF "TARGET_FMA || TARGET_FMA4")]) + (define_insn "fma_fmadd_" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (match_operand:FMAMODE 1 "" "%0,0,v,x,x") - (match_operand:FMAMODE 2 "" ",v,,x,m") - (match_operand:FMAMODE 3 "" "v,,0,xm,x")))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "" "%0,0,v,x,x") + (match_operand:FMAMODE_NOVF512 2 "" ",v,,x,m") + (match_operand:FMAMODE_NOVF512 3 "" "v,,0,xm,x")))] " && " "@ vfmadd132\t{%2, %3, %0|%0, %3, %2} @@ -2788,6 +2792,21 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) +(define_insn "fma_fmadd_" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (match_operand:VF_512 1 "" "%0,0,v") + (match_operand:VF_512 2 "" ",v,") + (match_operand:VF_512 3 "" "v,,0")))] + " && " + "@ + vfmadd132\t{%2, %3, %0|%0, %3, %2} + vfmadd213\t{%3, %2, %0|%0, %2, %3} + vfmadd231\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "")]) + (define_insn "avx512f_fmadd__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -2821,12 +2840,12 @@ (set_attr "mode" "")]) (define_insn "fma_fmsub_" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (match_operand:FMAMODE 1 "" "%0, 0, v, x,x") - (match_operand:FMAMODE 2 "" ",v,,x,m") - (neg:FMAMODE - (match_operand:FMAMODE 3 "" "v,,0,xm,x"))))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "" "%0,0,v,x,x") + (match_operand:FMAMODE_NOVF512 2 "" ",v,,x,m") + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 3 "" "v,,0,xm,x"))))] " && " "@ vfmsub132\t{%2, %3, %0|%0, %3, %2} @@ -2838,6 +2857,22 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) +(define_insn "fma_fmsub_" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (match_operand:VF_512 1 "" "%0,0,v") + (match_operand:VF_512 2 "" ",v,") + (neg:VF_512 + (match_operand:VF_512 3 "" "v,,0"))))] + " && " + "@ + vfmsub132\t{%2, %3, %0|%0, %3, %2} + vfmsub213\t{%3, %2, %0|%0, %2, %3} + vfmsub231\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "")]) + (define_insn "avx512f_fmsub__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -2873,12 +2908,12 @@ (set_attr "mode" "")]) (define_insn "fma_fnmadd_" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (neg:FMAMODE - (match_operand:FMAMODE 1 "" "%0,0,v,x,x")) - (match_operand:FMAMODE 2 "" ",v,,x,m") - (match_operand:FMAMODE 3 "" "v,,0,xm,x")))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "" "%0,0,v,x,x")) + (match_operand:FMAMODE_NOVF512 2 "" ",v,,x,m") + (match_operand:FMAMODE_NOVF512 3 "" "v,,0,xm,x")))] " && " "@ vfnmadd132\t{%2, %3, %0|%0, %3, %2} @@ -2890,6 +2925,22 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) +(define_insn "fma_fnmadd_" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (neg:VF_512 + (match_operand:VF_512 1 "" "%0,0,v")) + (match_operand:VF_512 2 "" ",v,") + (match_operand:VF_512 3 "" "v,,0")))] + " && " + "@ + vfnmadd132\t{%2, %3, %0|%0, %3, %2} + vfnmadd213\t{%3, %2, %0|%0, %2, %3} + vfnmadd231\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "")]) + (define_insn "avx512f_fnmadd__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -2925,13 +2976,13 @@ (set_attr "mode" "")]) (define_insn "fma_fnmsub_" - [(set (match_operand:FMAMODE 0 "register_operand" "=v,v,v,x,x") - (fma:FMAMODE - (neg:FMAMODE - (match_operand:FMAMODE 1 "" "%0,0,v,x,x")) - (match_operand:FMAMODE 2 "" ",v,,x,m") - (neg:FMAMODE - (match_operand:FMAMODE 3 "" "v,,0,xm,x"))))] + [(set (match_operand:FMAMODE_NOVF512 0 "register_operand" "=v,v,v,x,x") + (fma:FMAMODE_NOVF512 + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 1 "" "%0,0,v,x,x")) + (match_operand:FMAMODE_NOVF512 2 "" ",v,,x,m") + (neg:FMAMODE_NOVF512 + (match_operand:FMAMODE_NOVF512 3 "" "v,,0,xm,x"))))] " && " "@ vfnmsub132\t{%2, %3, %0|%0, %3, %2} @@ -2943,6 +2994,23 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) +(define_insn "fma_fnmsub_" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (fma:VF_512 + (neg:VF_512 + (match_operand:VF_512 1 "" "%0,0,v")) + (match_operand:VF_512 2 "" ",v,") + (neg:VF_512 + (match_operand:VF_512 3 "" "v,,0"))))] + " && " + "@ + vfnmsub132\t{%2, %3, %0|%0, %3, %2} + vfnmsub213\t{%3, %2, %0|%0, %2, %3} + vfnmsub231\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "")]) + (define_insn "avx512f_fnmsub__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -3014,11 +3082,11 @@ }) (define_insn "fma_fmaddsub_" - [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") - (unspec:VF - [(match_operand:VF 1 "" "%0,0,v,x,x") - (match_operand:VF 2 "" ",v,,x,m") - (match_operand:VF 3 "" "v,,0,xm,x")] + [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x") + (unspec:VF_128_256 + [(match_operand:VF_128_256 1 "" "%0,0,v,x,x") + (match_operand:VF_128_256 2 "" ",v,,x,m") + (match_operand:VF_128_256 3 "" "v,,0,xm,x")] UNSPEC_FMADDSUB))] "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && && " "@ @@ -3031,6 +3099,22 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) +(define_insn "fma_fmaddsub_" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (unspec:VF_512 + [(match_operand:VF_512 1 "" "%0,0,v") + (match_operand:VF_512 2 "" ",v,") + (match_operand:VF_512 3 "" "v,,0")] + UNSPEC_FMADDSUB))] + "TARGET_AVX512F && && " + "@ + vfmaddsub132\t{%2, %3, %0|%0, %3, %2} + vfmaddsub213\t{%3, %2, %0|%0, %2, %3} + vfmaddsub231\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "")]) + (define_insn "avx512f_fmaddsub__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 @@ -3066,12 +3150,12 @@ (set_attr "mode" "")]) (define_insn "fma_fmsubadd_" - [(set (match_operand:VF 0 "register_operand" "=v,v,v,x,x") - (unspec:VF - [(match_operand:VF 1 "" "%0,0,v,x,x") - (match_operand:VF 2 "" ",v,,x,m") - (neg:VF - (match_operand:VF 3 "" "v,,0,xm,x"))] + [(set (match_operand:VF_128_256 0 "register_operand" "=v,v,v,x,x") + (unspec:VF_128_256 + [(match_operand:VF_128_256 1 "" "%0,0,v,x,x") + (match_operand:VF_128_256 2 "" ",v,,x,m") + (neg:VF_128_256 + (match_operand:VF_128_256 3 "" "v,,0,xm,x"))] UNSPEC_FMADDSUB))] "(TARGET_FMA || TARGET_FMA4 || TARGET_AVX512F) && && " "@ @@ -3084,6 +3168,23 @@ (set_attr "type" "ssemuladd") (set_attr "mode" "")]) +(define_insn "fma_fmsubadd_" + [(set (match_operand:VF_512 0 "register_operand" "=v,v,v") + (unspec:VF_512 + [(match_operand:VF_512 1 "" "%0,0,v") + (match_operand:VF_512 2 "" ",v,") + (neg:VF_512 + (match_operand:VF_512 3 "" "v,,0"))] + UNSPEC_FMADDSUB))] + "TARGET_AVX512F && && " + "@ + vfmsubadd132\t{%2, %3, %0|%0, %3, %2} + vfmsubadd213\t{%3, %2, %0|%0, %2, %3} + vfmsubadd231\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "fma_avx512f,fma_avx512f,fma_avx512f") + (set_attr "type" "ssemuladd") + (set_attr "mode" "")]) + (define_insn "avx512f_fmsubadd__mask" [(set (match_operand:VF_512 0 "register_operand" "=v,v") (vec_merge:VF_512 -- 2.7.4