From 4265ab00952bad0669493698c43f6c88a7fea200 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 31 May 2023 14:23:35 +0200 Subject: [PATCH] radv: merge all FS user SGPRs into one using packed arguments Much cleaner and this will allow us to add more arguments easily. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/nir/radv_nir_lower_abi.c | 8 ++-- src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c | 6 ++- src/amd/vulkan/radv_cmd_buffer.c | 45 ++++++++--------------- src/amd/vulkan/radv_shader.h | 11 ++++-- src/amd/vulkan/radv_shader_args.c | 28 +++++++++----- src/amd/vulkan/radv_shader_args.h | 4 +- 6 files changed, 52 insertions(+), 50 deletions(-) diff --git a/src/amd/vulkan/nir/radv_nir_lower_abi.c b/src/amd/vulkan/nir/radv_nir_lower_abi.c index 9e17f58..b22e861 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_abi.c +++ b/src/amd/vulkan/nir/radv_nir_lower_abi.c @@ -334,7 +334,7 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) } case nir_intrinsic_load_rasterization_samples_amd: if (s->pl_key->dynamic_rasterization_samples) { - replacement = ac_nir_load_arg(b, &s->args->ac, s->args->ps_num_samples); + replacement = GET_SGPR_FIELD_NIR(s->args->ps_state, PS_STATE_NUM_SAMPLES); } else { replacement = nir_imm_int(b, s->pl_key->ps.num_samples); } @@ -464,8 +464,10 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) } case nir_intrinsic_load_poly_line_smooth_enabled: if (s->pl_key->dynamic_line_rast_mode) { - replacement = nir_ieq_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ps_line_rast_mode), - VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT); + nir_ssa_def *line_rast_mode = + GET_SGPR_FIELD_NIR(s->args->ps_state, PS_STATE_LINE_RAST_MODE); + replacement = + nir_ieq_imm(b, line_rast_mode, VK_LINE_RASTERIZATION_MODE_RECTANGULAR_SMOOTH_EXT); } else { replacement = nir_imm_bool(b, s->pl_key->ps.line_smooth_enabled); } diff --git a/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c b/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c index ccff089..07423d6 100644 --- a/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c +++ b/src/amd/vulkan/nir/radv_nir_lower_fs_intrinsics.c @@ -56,8 +56,10 @@ radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage * nir_ssa_def *def = NULL; if (info->ps.uses_sample_shading || key->ps.sample_shading_enable) { /* gl_SampleMaskIn[0] = (SampleCoverage & (PsIterMask << gl_SampleID)). */ - nir_ssa_def *ps_iter_mask = - nir_load_scalar_arg_amd(&b, 1, .base = args->ps_iter_mask.arg_index); + nir_ssa_def *ps_state = + nir_load_scalar_arg_amd(&b, 1, .base = args->ps_state.arg_index); + nir_ssa_def *ps_iter_mask = nir_ubfe_imm(&b, ps_state, PS_STATE_PS_ITER_MASK__SHIFT, + util_bitcount(PS_STATE_PS_ITER_MASK__MASK)); nir_ssa_def *sample_id = nir_load_sample_id(&b); def = nir_iand(&b, sample_coverage, nir_ishl(&b, ps_iter_mask, sample_id)); } else { diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 470a4eb..cb5731b 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -6640,14 +6640,10 @@ radv_bind_fragment_shader(struct radv_cmd_buffer *cmd_buffer, const struct radv_ cmd_buffer->sample_positions_needed = true; } - /* Re-emit the rasterization samples state because the SGPR idx can be different. */ - if (radv_get_user_sgpr(ps, AC_UD_PS_NUM_SAMPLES)->sgpr_idx != -1) { - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES; - } - - /* Re-emit the line rasterization mode state because the SGPR idx can be different. */ - if (radv_get_user_sgpr(ps, AC_UD_PS_LINE_RAST_MODE)->sgpr_idx != -1) { - cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE; + /* Re-emit the FS state because the SGPR idx can be different. */ + if (radv_get_user_sgpr(ps, AC_UD_PS_STATE)->sgpr_idx != -1) { + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES | + RADV_CMD_DIRTY_DYNAMIC_LINE_RASTERIZATION_MODE; } /* Re-emit the conservative rasterization mode because inner coverage is different. */ @@ -9071,29 +9067,20 @@ radv_emit_fs_state(struct radv_cmd_buffer *cmd_buffer) if (!ps) return; - loc = radv_get_user_sgpr(ps, AC_UD_PS_NUM_SAMPLES); - if (loc->sgpr_idx != -1) { - const unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); - const uint32_t base_reg = ps->info.user_data_0; - - radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, rasterization_samples); - } - - loc = radv_get_user_sgpr(ps, AC_UD_PS_ITER_MASK); - if (loc->sgpr_idx != -1) { - const unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer); - const uint16_t ps_iter_mask = ac_get_ps_iter_mask(ps_iter_samples); - const uint32_t base_reg = ps->info.user_data_0; - - radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, ps_iter_mask); - } + loc = radv_get_user_sgpr(ps, AC_UD_PS_STATE); + if (loc->sgpr_idx == -1) + return; + assert(loc->num_sgprs == 1); - loc = radv_get_user_sgpr(ps, AC_UD_PS_LINE_RAST_MODE); - if (loc->sgpr_idx != -1) { - const uint32_t base_reg = ps->info.user_data_0; + const unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); + const unsigned ps_iter_samples = radv_get_ps_iter_samples(cmd_buffer); + const uint16_t ps_iter_mask = ac_get_ps_iter_mask(ps_iter_samples); + const uint32_t base_reg = ps->info.user_data_0; + const unsigned ps_state = SET_SGPR_FIELD(PS_STATE_NUM_SAMPLES, rasterization_samples) | + SET_SGPR_FIELD(PS_STATE_PS_ITER_MASK, ps_iter_mask) | + SET_SGPR_FIELD(PS_STATE_LINE_RAST_MODE, d->vk.rs.line.mode); - radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, d->vk.rs.line.mode); - } + radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, ps_state); } static void diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h index a2477cf..597970e 100644 --- a/src/amd/vulkan/radv_shader.h +++ b/src/amd/vulkan/radv_shader.h @@ -168,9 +168,7 @@ enum radv_ud_index { AC_UD_VS_PROLOG_INPUTS, AC_UD_VS_MAX_UD, AC_UD_PS_EPILOG_PC, - AC_UD_PS_NUM_SAMPLES, - AC_UD_PS_LINE_RAST_MODE, - AC_UD_PS_ITER_MASK, + AC_UD_PS_STATE, AC_UD_PS_MAX_UD, AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START, AC_UD_CS_SBT_DESCRIPTORS, @@ -197,6 +195,13 @@ enum radv_ud_index { #define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__SHIFT 6 #define TCS_OFFCHIP_LAYOUT_NUM_PATCHES__MASK 0xff +#define PS_STATE_NUM_SAMPLES__SHIFT 0 +#define PS_STATE_NUM_SAMPLES__MASK 0xf +#define PS_STATE_LINE_RAST_MODE__SHIFT 4 +#define PS_STATE_LINE_RAST_MODE__MASK 0x3 +#define PS_STATE_PS_ITER_MASK__SHIFT 6 +#define PS_STATE_PS_ITER_MASK__MASK 0xffff + struct radv_streamout_info { uint16_t num_outputs; uint16_t strides[MAX_SO_BUFFERS]; diff --git a/src/amd/vulkan/radv_shader_args.c b/src/amd/vulkan/radv_shader_args.c index f257a18..92a2b88 100644 --- a/src/amd/vulkan/radv_shader_args.c +++ b/src/amd/vulkan/radv_shader_args.c @@ -347,6 +347,22 @@ radv_declare_rt_shader_args(enum amd_gfx_level gfx_level, struct radv_shader_arg ac_add_arg(&args->ac, AC_ARG_VGPR, 1, AC_ARG_INT, &args->ac.rt_dynamic_callable_stack_base); } +static bool +radv_ps_needs_state_sgpr(const struct radv_shader_info *info, const struct radv_pipeline_key *key) +{ + if (info->ps.needs_sample_positions && key->dynamic_rasterization_samples) + return true; + + if (key->dynamic_line_rast_mode) + return true; + + if (info->ps.reads_sample_mask_in && + (info->ps.uses_sample_shading || key->ps.sample_shading_enable)) + return true; + + return false; +} + static void declare_shader_args(const struct radv_device *device, const struct radv_pipeline_key *key, const struct radv_shader_info *info, gl_shader_stage stage, @@ -640,16 +656,8 @@ declare_shader_args(const struct radv_device *device, const struct radv_pipeline add_ud_arg(args, 1, AC_ARG_INT, &args->ps_epilog_pc, AC_UD_PS_EPILOG_PC); } - if (info->ps.needs_sample_positions && key->dynamic_rasterization_samples) { - add_ud_arg(args, 1, AC_ARG_INT, &args->ps_num_samples, AC_UD_PS_NUM_SAMPLES); - } - - if (key->dynamic_line_rast_mode) - add_ud_arg(args, 1, AC_ARG_INT, &args->ps_line_rast_mode, AC_UD_PS_LINE_RAST_MODE); - - if (info->ps.reads_sample_mask_in && (info->ps.uses_sample_shading || - key->ps.sample_shading_enable)) - add_ud_arg(args, 1, AC_ARG_INT, &args->ps_iter_mask, AC_UD_PS_ITER_MASK); + if (radv_ps_needs_state_sgpr(info, key)) + add_ud_arg(args, 1, AC_ARG_INT, &args->ps_state, AC_UD_PS_STATE); ac_add_arg(&args->ac, AC_ARG_SGPR, 1, AC_ARG_INT, &args->ac.prim_mask); if (args->explicit_scratch_args && gfx_level < GFX11) { diff --git a/src/amd/vulkan/radv_shader_args.h b/src/amd/vulkan/radv_shader_args.h index 3095b7d..cc4eb82 100644 --- a/src/amd/vulkan/radv_shader_args.h +++ b/src/amd/vulkan/radv_shader_args.h @@ -59,9 +59,7 @@ struct radv_shader_args { /* Fragment shaders */ struct ac_arg ps_epilog_pc; - struct ac_arg ps_num_samples; - struct ac_arg ps_line_rast_mode; - struct ac_arg ps_iter_mask; + struct ac_arg ps_state; struct ac_arg prolog_inputs; struct ac_arg vs_inputs[MAX_VERTEX_ATTRIBS]; -- 2.7.4