From 42594600095f03244a674fecdd2b5f6da2441180 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 14 Jan 2015 15:09:19 +1000 Subject: [PATCH] drm/nouveau/mmu: namespace + nvidia gpu names (no binary change) The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. A comparison of objdump disassemblies proves no code changes. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/core/os.h | 1 + drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h | 1 + drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h | 161 ++++++++------------ drivers/gpu/drm/nouveau/nvkm/core/engctx.c | 1 + drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c | 4 +- drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c | 18 +-- drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c | 16 +- drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c | 2 + drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild | 2 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c | 169 ++++++++++----------- .../nouveau/nvkm/subdev/mmu/{nvc0.c => gf100.c} | 92 ++++++----- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c | 56 +++---- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h | 6 +- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c | 56 ++++--- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c | 60 ++++---- drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c | 64 ++++---- 29 files changed, 351 insertions(+), 374 deletions(-) rename drivers/gpu/drm/nouveau/nvkm/subdev/mmu/{nvc0.c => gf100.c} (75%) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h index 7894ff5..4230865 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/core/os.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/core/os.h @@ -240,5 +240,6 @@ #define nvc0_pte_storage_type_map gf100_pte_storage_type_map #define nouveau_fuse nvkm_fuse #define nouveau_mc nvkm_mc +#define nouveau_mmu nvkm_mmu #endif diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h index 639d0fd..92cfcf5 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/ce.h @@ -1,5 +1,6 @@ #ifndef __NVKM_CE_H__ #define __NVKM_CE_H__ +#include void nva3_ce_intr(struct nouveau_subdev *); diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h index 2c3b299..3a53687 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/mmu.h @@ -1,72 +1,44 @@ -/* - * Copyright 2010 Red Hat Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: Ben Skeggs - */ - -#ifndef __NOUVEAU_MMU_H__ -#define __NOUVEAU_MMU_H__ - -#include +#ifndef __NVKM_MMU_H__ +#define __NVKM_MMU_H__ #include -#include #include +struct nvkm_device; +struct nvkm_mem; -struct nouveau_vm_pgt { - struct nouveau_gpuobj *obj[2]; +struct nvkm_vm_pgt { + struct nvkm_gpuobj *obj[2]; u32 refcount[2]; }; -struct nouveau_vm_pgd { +struct nvkm_vm_pgd { struct list_head head; - struct nouveau_gpuobj *obj; + struct nvkm_gpuobj *obj; }; -struct nouveau_gpuobj; -struct nouveau_mem; - -struct nouveau_vma { +struct nvkm_vma { struct list_head head; int refcount; - struct nouveau_vm *vm; - struct nouveau_mm_node *node; + struct nvkm_vm *vm; + struct nvkm_mm_node *node; u64 offset; u32 access; }; -struct nouveau_vm { - struct nouveau_mmu *mmu; - struct nouveau_mm mm; +struct nvkm_vm { + struct nvkm_mmu *mmu; + struct nvkm_mm mm; struct kref refcount; struct list_head pgd_list; atomic_t engref[NVDEV_SUBDEV_NR]; - struct nouveau_vm_pgt *pgt; + struct nvkm_vm_pgt *pgt; u32 fpde; u32 lpde; }; -struct nouveau_mmu { - struct nouveau_subdev base; +struct nvkm_mmu { + struct nvkm_subdev base; u64 limit; u8 dma_bits; @@ -74,62 +46,59 @@ struct nouveau_mmu { u8 spg_shift; u8 lpg_shift; - int (*create)(struct nouveau_mmu *, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **); + int (*create)(struct nvkm_mmu *, u64 offset, u64 length, + u64 mm_offset, struct nvkm_vm **); - void (*map_pgt)(struct nouveau_gpuobj *pgd, u32 pde, - struct nouveau_gpuobj *pgt[2]); - void (*map)(struct nouveau_vma *, struct nouveau_gpuobj *, - struct nouveau_mem *, u32 pte, u32 cnt, + void (*map_pgt)(struct nvkm_gpuobj *pgd, u32 pde, + struct nvkm_gpuobj *pgt[2]); + void (*map)(struct nvkm_vma *, struct nvkm_gpuobj *, + struct nvkm_mem *, u32 pte, u32 cnt, u64 phys, u64 delta); - void (*map_sg)(struct nouveau_vma *, struct nouveau_gpuobj *, - struct nouveau_mem *, u32 pte, u32 cnt, dma_addr_t *); - void (*unmap)(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt); - void (*flush)(struct nouveau_vm *); + void (*map_sg)(struct nvkm_vma *, struct nvkm_gpuobj *, + struct nvkm_mem *, u32 pte, u32 cnt, dma_addr_t *); + void (*unmap)(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt); + void (*flush)(struct nvkm_vm *); }; -static inline struct nouveau_mmu * -nouveau_mmu(void *obj) +static inline struct nvkm_mmu * +nvkm_mmu(void *obj) { - return (void *)nouveau_subdev(obj, NVDEV_SUBDEV_MMU); + return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_MMU); } -#define nouveau_mmu_create(p,e,o,i,f,d) \ - nouveau_subdev_create((p), (e), (o), 0, (i), (f), (d)) -#define nouveau_mmu_destroy(p) \ - nouveau_subdev_destroy(&(p)->base) -#define nouveau_mmu_init(p) \ - nouveau_subdev_init(&(p)->base) -#define nouveau_mmu_fini(p,s) \ - nouveau_subdev_fini(&(p)->base, (s)) - -#define _nouveau_mmu_dtor _nouveau_subdev_dtor -#define _nouveau_mmu_init _nouveau_subdev_init -#define _nouveau_mmu_fini _nouveau_subdev_fini - -extern struct nouveau_oclass nv04_mmu_oclass; -extern struct nouveau_oclass nv41_mmu_oclass; -extern struct nouveau_oclass nv44_mmu_oclass; -extern struct nouveau_oclass nv50_mmu_oclass; -extern struct nouveau_oclass nvc0_mmu_oclass; - -int nv04_vm_create(struct nouveau_mmu *, u64, u64, u64, - struct nouveau_vm **); -void nv04_mmu_dtor(struct nouveau_object *); - -/* nouveau_vm.c */ -int nouveau_vm_create(struct nouveau_mmu *, u64 offset, u64 length, - u64 mm_offset, u32 block, struct nouveau_vm **); -int nouveau_vm_new(struct nouveau_device *, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **); -int nouveau_vm_ref(struct nouveau_vm *, struct nouveau_vm **, - struct nouveau_gpuobj *pgd); -int nouveau_vm_get(struct nouveau_vm *, u64 size, u32 page_shift, - u32 access, struct nouveau_vma *); -void nouveau_vm_put(struct nouveau_vma *); -void nouveau_vm_map(struct nouveau_vma *, struct nouveau_mem *); -void nouveau_vm_map_at(struct nouveau_vma *, u64 offset, struct nouveau_mem *); -void nouveau_vm_unmap(struct nouveau_vma *); -void nouveau_vm_unmap_at(struct nouveau_vma *, u64 offset, u64 length); - +#define nvkm_mmu_create(p,e,o,i,f,d) \ + nvkm_subdev_create((p), (e), (o), 0, (i), (f), (d)) +#define nvkm_mmu_destroy(p) \ + nvkm_subdev_destroy(&(p)->base) +#define nvkm_mmu_init(p) \ + nvkm_subdev_init(&(p)->base) +#define nvkm_mmu_fini(p,s) \ + nvkm_subdev_fini(&(p)->base, (s)) + +#define _nvkm_mmu_dtor _nvkm_subdev_dtor +#define _nvkm_mmu_init _nvkm_subdev_init +#define _nvkm_mmu_fini _nvkm_subdev_fini + +extern struct nvkm_oclass nv04_mmu_oclass; +extern struct nvkm_oclass nv41_mmu_oclass; +extern struct nvkm_oclass nv44_mmu_oclass; +extern struct nvkm_oclass nv50_mmu_oclass; +extern struct nvkm_oclass gf100_mmu_oclass; + +int nv04_vm_create(struct nvkm_mmu *, u64, u64, u64, + struct nvkm_vm **); +void nv04_mmu_dtor(struct nvkm_object *); + +int nvkm_vm_create(struct nvkm_mmu *, u64 offset, u64 length, u64 mm_offset, + u32 block, struct nvkm_vm **); +int nvkm_vm_new(struct nvkm_device *, u64 offset, u64 length, u64 mm_offset, + struct nvkm_vm **); +int nvkm_vm_ref(struct nvkm_vm *, struct nvkm_vm **, struct nvkm_gpuobj *pgd); +int nvkm_vm_get(struct nvkm_vm *, u64 size, u32 page_shift, u32 access, + struct nvkm_vma *); +void nvkm_vm_put(struct nvkm_vma *); +void nvkm_vm_map(struct nvkm_vma *, struct nvkm_mem *); +void nvkm_vm_map_at(struct nvkm_vma *, u64 offset, struct nvkm_mem *); +void nvkm_vm_unmap(struct nvkm_vma *); +void nvkm_vm_unmap_at(struct nvkm_vma *, u64 offset, u64 length); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c index a9df07a..fb2acbc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/engctx.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/engctx.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include +#include #include static inline int diff --git a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c index 0c5cb55..2eba801 100644 --- a/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c +++ b/drivers/gpu/drm/nouveau/nvkm/core/gpuobj.c @@ -22,6 +22,7 @@ * Authors: Ben Skeggs */ #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c index b193b5f..b14617a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/ce/nva3.c @@ -30,6 +30,7 @@ #include #include +#include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c index 165271c..adf9c27 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c @@ -76,7 +76,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; @@ -120,7 +120,7 @@ gm100_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gm107_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; #if 0 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c index 2363a58..6cd796c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c @@ -76,7 +76,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -109,7 +109,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -142,7 +142,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -174,7 +174,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -207,7 +207,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -239,7 +239,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -271,7 +271,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvc0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -304,7 +304,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -336,7 +336,7 @@ nvc0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gf100_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gf100_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = nvc0_fifo_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c index 9ade562..64aee47 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c @@ -76,7 +76,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -110,7 +110,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -144,7 +144,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = gk104_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -172,7 +172,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk20a_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gk20a_bar_oclass; device->oclass[NVDEV_ENGINE_DMAOBJ ] = nvd0_dmaeng_oclass; device->oclass[NVDEV_ENGINE_FIFO ] = gk20a_fifo_oclass; @@ -200,7 +200,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -234,7 +234,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nvd0_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -268,7 +268,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; @@ -301,7 +301,7 @@ nve0_identify(struct nouveau_device *device) device->oclass[NVDEV_SUBDEV_LTC ] = gk104_ltc_oclass; device->oclass[NVDEV_SUBDEV_IBUS ] = &gk104_ibus_oclass; device->oclass[NVDEV_SUBDEV_INSTMEM] = nv50_instmem_oclass; - device->oclass[NVDEV_SUBDEV_MMU ] = &nvc0_mmu_oclass; + device->oclass[NVDEV_SUBDEV_MMU ] = &gf100_mmu_oclass; device->oclass[NVDEV_SUBDEV_BAR ] = &gf100_bar_oclass; device->oclass[NVDEV_SUBDEV_PMU ] = nv108_pmu_oclass; device->oclass[NVDEV_SUBDEV_VOLT ] = &nv40_volt_oclass; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c index e1500f7..741f4a7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/dmaobj/base.c @@ -24,6 +24,7 @@ #include #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c index 604cb52..be02934 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c @@ -23,6 +23,7 @@ */ #include +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c index 8b7d879..2798d26 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c @@ -20,6 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include #define CP_FLAG_CLEAR 0 diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c index 9cc5c25..6b3341f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.c @@ -23,6 +23,7 @@ */ #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c index 3995d2c..cea90df 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/xtensa.c @@ -20,6 +20,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include +#include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c index 4c6d238..12a1aeb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.c @@ -23,6 +23,7 @@ */ #include "priv.h" +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c index 5a6c2b7..d51aa02 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c @@ -23,6 +23,8 @@ */ #include "gf100.h" +#include + extern const u8 gf100_pte_storage_type_map[256]; bool diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c index 6c0b82f..09ebb94 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c @@ -25,6 +25,8 @@ */ #include "nv04.h" +#include + void nv30_fb_tile_init(struct nvkm_fb *pfb, int i, u32 addr, u32 size, u32 pitch, u32 flags, struct nvkm_fb_tile *tile) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c index 48fd5a5..0480ce5 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c @@ -24,6 +24,7 @@ #include "nv50.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c index 6cf526b..5f30db1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk20a.c @@ -21,6 +21,8 @@ */ #include "priv.h" +#include + struct gk20a_mem { struct nvkm_mem base; void *cpuaddr; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c index 8bb7e43..fbae05d 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.c @@ -23,6 +23,8 @@ */ #include "priv.h" +#include + static int nv1a_ram_create(struct nvkm_object *parent, struct nvkm_object *engine, struct nvkm_oclass *oclass, void *data, u32 size, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c index 14f5ba5..d2c81dd 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c @@ -24,6 +24,7 @@ #include "nv50.h" #include "ramseq.h" +#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild index 729e27f..012c9db 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/Kbuild @@ -3,4 +3,4 @@ nvkm-y += nvkm/subdev/mmu/nv04.o nvkm-y += nvkm/subdev/mmu/nv41.o nvkm-y += nvkm/subdev/mmu/nv44.o nvkm-y += nvkm/subdev/mmu/nv50.o -nvkm-y += nvkm/subdev/mmu/nvc0.o +nvkm-y += nvkm/subdev/mmu/gf100.o diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c index e3cb186..277b6ec 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.c @@ -21,19 +21,17 @@ * * Authors: Ben Skeggs */ +#include +#include #include -#include - -#include -#include void -nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) +nvkm_vm_map_at(struct nvkm_vma *vma, u64 delta, struct nvkm_mem *node) { - struct nouveau_vm *vm = vma->vm; - struct nouveau_mmu *mmu = vm->mmu; - struct nouveau_mm_node *r; + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_mm_node *r; int big = vma->node->type != mmu->spg_shift; u32 offset = vma->node->offset + (delta >> 12); u32 bits = vma->node->type - 12; @@ -48,7 +46,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) u32 num = r->length >> bits; while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; end = (pte + num); if (unlikely(end >= max)) @@ -73,11 +71,11 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node) } static void -nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, - struct nouveau_mem *mem) +nvkm_vm_map_sg_table(struct nvkm_vma *vma, u64 delta, u64 length, + struct nvkm_mem *mem) { - struct nouveau_vm *vm = vma->vm; - struct nouveau_mmu *mmu = vm->mmu; + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; int big = vma->node->type != mmu->spg_shift; u32 offset = vma->node->offset + (delta >> 12); u32 bits = vma->node->type - 12; @@ -91,7 +89,7 @@ nouveau_vm_map_sg_table(struct nouveau_vma *vma, u64 delta, u64 length, struct scatterlist *sg; for_each_sg(mem->sg->sgl, sg, mem->sg->nents, i) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; sglen = sg_dma_len(sg) >> PAGE_SHIFT; end = pte + sglen; @@ -131,11 +129,11 @@ finish: } static void -nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, - struct nouveau_mem *mem) +nvkm_vm_map_sg(struct nvkm_vma *vma, u64 delta, u64 length, + struct nvkm_mem *mem) { - struct nouveau_vm *vm = vma->vm; - struct nouveau_mmu *mmu = vm->mmu; + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; dma_addr_t *list = mem->pages; int big = vma->node->type != mmu->spg_shift; u32 offset = vma->node->offset + (delta >> 12); @@ -147,7 +145,7 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, u32 end, len; while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; end = (pte + num); if (unlikely(end >= max)) @@ -169,22 +167,22 @@ nouveau_vm_map_sg(struct nouveau_vma *vma, u64 delta, u64 length, } void -nouveau_vm_map(struct nouveau_vma *vma, struct nouveau_mem *node) +nvkm_vm_map(struct nvkm_vma *vma, struct nvkm_mem *node) { if (node->sg) - nouveau_vm_map_sg_table(vma, 0, node->size << 12, node); + nvkm_vm_map_sg_table(vma, 0, node->size << 12, node); else if (node->pages) - nouveau_vm_map_sg(vma, 0, node->size << 12, node); + nvkm_vm_map_sg(vma, 0, node->size << 12, node); else - nouveau_vm_map_at(vma, 0, node); + nvkm_vm_map_at(vma, 0, node); } void -nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) +nvkm_vm_unmap_at(struct nvkm_vma *vma, u64 delta, u64 length) { - struct nouveau_vm *vm = vma->vm; - struct nouveau_mmu *mmu = vm->mmu; + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; int big = vma->node->type != mmu->spg_shift; u32 offset = vma->node->offset + (delta >> 12); u32 bits = vma->node->type - 12; @@ -195,7 +193,7 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) u32 end, len; while (num) { - struct nouveau_gpuobj *pgt = vm->pgt[pde].obj[big]; + struct nvkm_gpuobj *pgt = vm->pgt[pde].obj[big]; end = (pte + num); if (unlikely(end >= max)) @@ -216,18 +214,18 @@ nouveau_vm_unmap_at(struct nouveau_vma *vma, u64 delta, u64 length) } void -nouveau_vm_unmap(struct nouveau_vma *vma) +nvkm_vm_unmap(struct nvkm_vma *vma) { - nouveau_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); + nvkm_vm_unmap_at(vma, 0, (u64)vma->node->length << 12); } static void -nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) +nvkm_vm_unmap_pgt(struct nvkm_vm *vm, int big, u32 fpde, u32 lpde) { - struct nouveau_mmu *mmu = vm->mmu; - struct nouveau_vm_pgd *vpgd; - struct nouveau_vm_pgt *vpgt; - struct nouveau_gpuobj *pgt; + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgd *vpgd; + struct nvkm_vm_pgt *vpgt; + struct nvkm_gpuobj *pgt; u32 pde; for (pde = fpde; pde <= lpde; pde++) { @@ -243,18 +241,18 @@ nouveau_vm_unmap_pgt(struct nouveau_vm *vm, int big, u32 fpde, u32 lpde) } mutex_unlock(&nv_subdev(mmu)->mutex); - nouveau_gpuobj_ref(NULL, &pgt); + nvkm_gpuobj_ref(NULL, &pgt); mutex_lock(&nv_subdev(mmu)->mutex); } } static int -nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) +nvkm_vm_map_pgt(struct nvkm_vm *vm, u32 pde, u32 type) { - struct nouveau_mmu *mmu = vm->mmu; - struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; - struct nouveau_vm_pgd *vpgd; - struct nouveau_gpuobj *pgt; + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; + struct nvkm_vm_pgd *vpgd; + struct nvkm_gpuobj *pgt; int big = (type != mmu->spg_shift); u32 pgt_size; int ret; @@ -263,8 +261,8 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) pgt_size *= 8; mutex_unlock(&nv_subdev(mmu)->mutex); - ret = nouveau_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000, - NVOBJ_FLAG_ZERO_ALLOC, &pgt); + ret = nvkm_gpuobj_new(nv_object(vm->mmu), NULL, pgt_size, 0x1000, + NVOBJ_FLAG_ZERO_ALLOC, &pgt); mutex_lock(&nv_subdev(mmu)->mutex); if (unlikely(ret)) return ret; @@ -272,7 +270,7 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) /* someone beat us to filling the PDE while we didn't have the lock */ if (unlikely(vpgt->refcount[big]++)) { mutex_unlock(&nv_subdev(mmu)->mutex); - nouveau_gpuobj_ref(NULL, &pgt); + nvkm_gpuobj_ref(NULL, &pgt); mutex_lock(&nv_subdev(mmu)->mutex); return 0; } @@ -286,18 +284,18 @@ nouveau_vm_map_pgt(struct nouveau_vm *vm, u32 pde, u32 type) } int -nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, - u32 access, struct nouveau_vma *vma) +nvkm_vm_get(struct nvkm_vm *vm, u64 size, u32 page_shift, u32 access, + struct nvkm_vma *vma) { - struct nouveau_mmu *mmu = vm->mmu; + struct nvkm_mmu *mmu = vm->mmu; u32 align = (1 << page_shift) >> 12; u32 msize = size >> 12; u32 fpde, lpde, pde; int ret; mutex_lock(&nv_subdev(mmu)->mutex); - ret = nouveau_mm_head(&vm->mm, 0, page_shift, msize, msize, align, - &vma->node); + ret = nvkm_mm_head(&vm->mm, 0, page_shift, msize, msize, align, + &vma->node); if (unlikely(ret != 0)) { mutex_unlock(&nv_subdev(mmu)->mutex); return ret; @@ -307,7 +305,7 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; for (pde = fpde; pde <= lpde; pde++) { - struct nouveau_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; + struct nvkm_vm_pgt *vpgt = &vm->pgt[pde - vm->fpde]; int big = (vma->node->type != mmu->spg_shift); if (likely(vpgt->refcount[big])) { @@ -315,11 +313,11 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, continue; } - ret = nouveau_vm_map_pgt(vm, pde, vma->node->type); + ret = nvkm_vm_map_pgt(vm, pde, vma->node->type); if (ret) { if (pde != fpde) - nouveau_vm_unmap_pgt(vm, big, fpde, pde - 1); - nouveau_mm_free(&vm->mm, &vma->node); + nvkm_vm_unmap_pgt(vm, big, fpde, pde - 1); + nvkm_mm_free(&vm->mm, &vma->node); mutex_unlock(&nv_subdev(mmu)->mutex); return ret; } @@ -327,17 +325,17 @@ nouveau_vm_get(struct nouveau_vm *vm, u64 size, u32 page_shift, mutex_unlock(&nv_subdev(mmu)->mutex); vma->vm = NULL; - nouveau_vm_ref(vm, &vma->vm, NULL); + nvkm_vm_ref(vm, &vma->vm, NULL); vma->offset = (u64)vma->node->offset << 12; vma->access = access; return 0; } void -nouveau_vm_put(struct nouveau_vma *vma) +nvkm_vm_put(struct nvkm_vma *vma) { - struct nouveau_vm *vm = vma->vm; - struct nouveau_mmu *mmu = vm->mmu; + struct nvkm_vm *vm = vma->vm; + struct nvkm_mmu *mmu = vm->mmu; u32 fpde, lpde; if (unlikely(vma->node == NULL)) @@ -346,18 +344,18 @@ nouveau_vm_put(struct nouveau_vma *vma) lpde = (vma->node->offset + vma->node->length - 1) >> mmu->pgt_bits; mutex_lock(&nv_subdev(mmu)->mutex); - nouveau_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde); - nouveau_mm_free(&vm->mm, &vma->node); + nvkm_vm_unmap_pgt(vm, vma->node->type != mmu->spg_shift, fpde, lpde); + nvkm_mm_free(&vm->mm, &vma->node); mutex_unlock(&nv_subdev(mmu)->mutex); - nouveau_vm_ref(NULL, &vma->vm, NULL); + nvkm_vm_ref(NULL, &vma->vm, NULL); } int -nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, - u64 mm_offset, u32 block, struct nouveau_vm **pvm) +nvkm_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset, + u32 block, struct nvkm_vm **pvm) { - struct nouveau_vm *vm; + struct nvkm_vm *vm; u64 mm_length = (offset + length) - mm_offset; int ret; @@ -377,8 +375,8 @@ nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, return -ENOMEM; } - ret = nouveau_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, - block >> 12); + ret = nvkm_mm_init(&vm->mm, mm_offset >> 12, mm_length >> 12, + block >> 12); if (ret) { vfree(vm->pgt); kfree(vm); @@ -391,18 +389,18 @@ nouveau_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, } int -nouveau_vm_new(struct nouveau_device *device, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) +nvkm_vm_new(struct nvkm_device *device, u64 offset, u64 length, u64 mm_offset, + struct nvkm_vm **pvm) { - struct nouveau_mmu *mmu = nouveau_mmu(device); + struct nvkm_mmu *mmu = nvkm_mmu(device); return mmu->create(mmu, offset, length, mm_offset, pvm); } static int -nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) +nvkm_vm_link(struct nvkm_vm *vm, struct nvkm_gpuobj *pgd) { - struct nouveau_mmu *mmu = vm->mmu; - struct nouveau_vm_pgd *vpgd; + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgd *vpgd; int i; if (!pgd) @@ -412,7 +410,7 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) if (!vpgd) return -ENOMEM; - nouveau_gpuobj_ref(pgd, &vpgd->obj); + nvkm_gpuobj_ref(pgd, &vpgd->obj); mutex_lock(&nv_subdev(mmu)->mutex); for (i = vm->fpde; i <= vm->lpde; i++) @@ -423,11 +421,11 @@ nouveau_vm_link(struct nouveau_vm *vm, struct nouveau_gpuobj *pgd) } static void -nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) +nvkm_vm_unlink(struct nvkm_vm *vm, struct nvkm_gpuobj *mpgd) { - struct nouveau_mmu *mmu = vm->mmu; - struct nouveau_vm_pgd *vpgd, *tmp; - struct nouveau_gpuobj *pgd = NULL; + struct nvkm_mmu *mmu = vm->mmu; + struct nvkm_vm_pgd *vpgd, *tmp; + struct nvkm_gpuobj *pgd = NULL; if (!mpgd) return; @@ -443,30 +441,29 @@ nouveau_vm_unlink(struct nouveau_vm *vm, struct nouveau_gpuobj *mpgd) } mutex_unlock(&nv_subdev(mmu)->mutex); - nouveau_gpuobj_ref(NULL, &pgd); + nvkm_gpuobj_ref(NULL, &pgd); } static void -nouveau_vm_del(struct kref *kref) +nvkm_vm_del(struct kref *kref) { - struct nouveau_vm *vm = container_of(kref, typeof(*vm), refcount); - struct nouveau_vm_pgd *vpgd, *tmp; + struct nvkm_vm *vm = container_of(kref, typeof(*vm), refcount); + struct nvkm_vm_pgd *vpgd, *tmp; list_for_each_entry_safe(vpgd, tmp, &vm->pgd_list, head) { - nouveau_vm_unlink(vm, vpgd->obj); + nvkm_vm_unlink(vm, vpgd->obj); } - nouveau_mm_fini(&vm->mm); + nvkm_mm_fini(&vm->mm); vfree(vm->pgt); kfree(vm); } int -nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, - struct nouveau_gpuobj *pgd) +nvkm_vm_ref(struct nvkm_vm *ref, struct nvkm_vm **ptr, struct nvkm_gpuobj *pgd) { if (ref) { - int ret = nouveau_vm_link(ref, pgd); + int ret = nvkm_vm_link(ref, pgd); if (ret) return ret; @@ -474,8 +471,8 @@ nouveau_vm_ref(struct nouveau_vm *ref, struct nouveau_vm **ptr, } if (*ptr) { - nouveau_vm_unlink(*ptr, pgd); - kref_put(&(*ptr)->refcount, nouveau_vm_del); + nvkm_vm_unlink(*ptr, pgd); + kref_put(&(*ptr)->refcount, nvkm_vm_del); } *ptr = ref; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c similarity index 75% rename from drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c rename to drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c index bd695c5..294cda3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nvc0.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c @@ -21,25 +21,23 @@ * * Authors: Ben Skeggs */ - -#include -#include - -#include -#include #include -#include #include +#include +#include +#include -struct nvc0_mmu_priv { - struct nouveau_mmu base; +#include + +struct gf100_mmu_priv { + struct nvkm_mmu base; }; /* Map from compressed to corresponding uncompressed storage type. * The value 0xff represents an invalid storage type. */ -const u8 nvc0_pte_storage_type_map[256] = +const u8 gf100_pte_storage_type_map[256] = { 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0xff, 0x01, /* 0x00 */ 0x01, 0x01, 0x01, 0xff, 0xff, 0xff, 0xff, 0xff, @@ -77,8 +75,7 @@ const u8 nvc0_pte_storage_type_map[256] = static void -nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, - struct nouveau_gpuobj *pgt[2]) +gf100_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 index, struct nvkm_gpuobj *pgt[2]) { u32 pde[2] = { 0, 0 }; @@ -92,7 +89,7 @@ nvc0_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 index, } static inline u64 -nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) { phys >>= 8; @@ -102,21 +99,20 @@ nvc0_vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) phys |= ((u64)target << 32); phys |= ((u64)memtype << 36); - return phys; } static void -nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +gf100_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) { u64 next = 1 << (vma->node->type - 8); - phys = nvc0_vm_addr(vma, phys, mem->memtype, 0); + phys = gf100_vm_addr(vma, phys, mem->memtype, 0); pte <<= 3; if (mem->tag) { - struct nouveau_ltc *ltc = nouveau_ltc(vma->vm->mmu); + struct nvkm_ltc *ltc = nvkm_ltc(vma->vm->mmu); u32 tag = mem->tag->offset + (delta >> 17); phys |= (u64)tag << (32 + 12); next |= (u64)1 << (32 + 12); @@ -132,16 +128,16 @@ nvc0_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5; /* compressed storage types are invalid for system memory */ - u32 memtype = nvc0_pte_storage_type_map[mem->memtype & 0xff]; + u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff]; pte <<= 3; while (cnt--) { - u64 phys = nvc0_vm_addr(vma, *list++, memtype, target); + u64 phys = gf100_vm_addr(vma, *list++, memtype, target); nv_wo32(pgt, pte + 0, lower_32_bits(phys)); nv_wo32(pgt, pte + 4, upper_32_bits(phys)); pte += 8; @@ -149,7 +145,7 @@ nvc0_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +gf100_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte <<= 3; while (cnt--) { @@ -160,11 +156,11 @@ nvc0_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nvc0_vm_flush(struct nouveau_vm *vm) +gf100_vm_flush(struct nvkm_vm *vm) { - struct nvc0_mmu_priv *priv = (void *)vm->mmu; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_vm_pgd *vpgd; + struct gf100_mmu_priv *priv = (void *)vm->mmu; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_vm_pgd *vpgd; u32 type; bar->flush(bar); @@ -196,21 +192,21 @@ nvc0_vm_flush(struct nouveau_vm *vm) } static int -nvc0_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) +gf100_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mm_offset, + struct nvkm_vm **pvm) { - return nouveau_vm_create(mmu, offset, length, mm_offset, 4096, pvm); + return nvkm_vm_create(mmu, offset, length, mm_offset, 4096, pvm); } static int -nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +gf100_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nvc0_mmu_priv *priv; + struct gf100_mmu_priv *priv; int ret; - ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -220,22 +216,22 @@ nvc0_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.pgt_bits = 27 - 12; priv->base.spg_shift = 12; priv->base.lpg_shift = 17; - priv->base.create = nvc0_vm_create; - priv->base.map_pgt = nvc0_vm_map_pgt; - priv->base.map = nvc0_vm_map; - priv->base.map_sg = nvc0_vm_map_sg; - priv->base.unmap = nvc0_vm_unmap; - priv->base.flush = nvc0_vm_flush; + priv->base.create = gf100_vm_create; + priv->base.map_pgt = gf100_vm_map_pgt; + priv->base.map = gf100_vm_map; + priv->base.map_sg = gf100_vm_map_sg; + priv->base.unmap = gf100_vm_unmap; + priv->base.flush = gf100_vm_flush; return 0; } -struct nouveau_oclass -nvc0_mmu_oclass = { +struct nvkm_oclass +gf100_mmu_oclass = { .handle = NV_SUBDEV(MMU, 0xc0), - .ofuncs = &(struct nouveau_ofuncs) { - .ctor = nvc0_mmu_ctor, - .dtor = _nouveau_mmu_dtor, - .init = _nouveau_mmu_init, - .fini = _nouveau_mmu_fini, + .ofuncs = &(struct nvkm_ofuncs) { + .ctor = gf100_mmu_ctor, + .dtor = _nvkm_mmu_dtor, + .init = _nvkm_mmu_init, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c index a317d8f..fe93ea2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.c @@ -21,11 +21,11 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" +#include #include -#include "nv04.h" - #define NV04_PDMA_SIZE (128 * 1024 * 1024) #define NV04_PDMA_PAGE ( 4 * 1024) @@ -34,8 +34,8 @@ ******************************************************************************/ static void -nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv04_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { pte = 0x00008 + (pte * 4); while (cnt) { @@ -51,7 +51,7 @@ nv04_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv04_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte = 0x00008 + (pte * 4); while (cnt--) { @@ -61,7 +61,7 @@ nv04_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv04_vm_flush(struct nouveau_vm *vm) +nv04_vm_flush(struct nvkm_vm *vm) { } @@ -70,8 +70,8 @@ nv04_vm_flush(struct nouveau_vm *vm) ******************************************************************************/ int -nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart, - struct nouveau_vm **pvm) +nv04_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, u64 mmstart, + struct nvkm_vm **pvm) { return -EINVAL; } @@ -81,16 +81,16 @@ nv04_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, u64 mmstart, ******************************************************************************/ static int -nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv04_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv04_mmu_priv *priv; - struct nouveau_gpuobj *dma; + struct nvkm_gpuobj *dma; int ret; - ret = nouveau_mmu_create(parent, engine, oclass, "PCIGART", - "pcigart", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "PCIGART", + "pcigart", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -105,15 +105,15 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.unmap = nv04_vm_unmap; priv->base.flush = nv04_vm_flush; - ret = nouveau_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, - &priv->vm); + ret = nvkm_vm_create(&priv->base, 0, NV04_PDMA_SIZE, 0, 4096, + &priv->vm); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + - 8, 16, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (NV04_PDMA_SIZE / NV04_PDMA_PAGE) * 4 + 8, + 16, NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); dma = priv->vm->pgt[0].obj[0]; priv->vm->pgt[0].refcount[0] = 1; if (ret) @@ -125,27 +125,27 @@ nv04_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } void -nv04_mmu_dtor(struct nouveau_object *object) +nv04_mmu_dtor(struct nvkm_object *object) { struct nv04_mmu_priv *priv = (void *)object; if (priv->vm) { - nouveau_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); - nouveau_vm_ref(NULL, &priv->vm, NULL); + nvkm_gpuobj_ref(NULL, &priv->vm->pgt[0].obj[0]); + nvkm_vm_ref(NULL, &priv->vm, NULL); } if (priv->nullp) { pci_free_consistent(nv_device(priv)->pdev, 16 * 1024, priv->nullp, priv->null); } - nouveau_mmu_destroy(&priv->base); + nvkm_mmu_destroy(&priv->base); } -struct nouveau_oclass +struct nvkm_oclass nv04_mmu_oclass = { .handle = NV_SUBDEV(MMU, 0x04), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv04_mmu_ctor, .dtor = nv04_mmu_dtor, - .init = _nouveau_mmu_init, - .fini = _nouveau_mmu_fini, + .init = _nvkm_mmu_init, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h index 919b254..7bf6f4b 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.h @@ -4,8 +4,8 @@ #include struct nv04_mmu_priv { - struct nouveau_mmu base; - struct nouveau_vm *vm; + struct nvkm_mmu base; + struct nvkm_vm *vm; dma_addr_t null; void *nullp; }; @@ -13,7 +13,7 @@ struct nv04_mmu_priv { static inline struct nv04_mmu_priv * nv04_mmu(void *obj) { - return (void *)nouveau_mmu(obj); + return (void *)nvkm_mmu(obj); } #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c index 61af036..61ee3ab 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" +#include #include #include - #include -#include - -#include "nv04.h" #define NV41_GART_SIZE (512 * 1024 * 1024) #define NV41_GART_PAGE ( 4 * 1024) @@ -38,8 +36,8 @@ ******************************************************************************/ static void -nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { pte = pte * 4; while (cnt) { @@ -55,7 +53,7 @@ nv41_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte = pte * 4; while (cnt--) { @@ -65,7 +63,7 @@ nv41_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv41_vm_flush(struct nouveau_vm *vm) +nv41_vm_flush(struct nvkm_vm *vm) { struct nv04_mmu_priv *priv = (void *)vm->mmu; @@ -84,22 +82,22 @@ nv41_vm_flush(struct nouveau_vm *vm) ******************************************************************************/ static int -nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); + struct nvkm_device *device = nv_device(parent); struct nv04_mmu_priv *priv; int ret; if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || - !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { - return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, - data, size, pobject); + !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) { + return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, + data, size, pobject); } - ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", - "pciegart", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", + "pciegart", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -114,15 +112,15 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, priv->base.unmap = nv41_vm_unmap; priv->base.flush = nv41_vm_flush; - ret = nouveau_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, - &priv->vm); + ret = nvkm_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096, + &priv->vm); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV41_GART_SIZE / NV41_GART_PAGE) * 4, - 16, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16, + NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); priv->vm->pgt[0].refcount[0] = 1; if (ret) return ret; @@ -131,13 +129,13 @@ nv41_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv41_mmu_init(struct nouveau_object *object) +nv41_mmu_init(struct nvkm_object *object) { struct nv04_mmu_priv *priv = (void *)object; - struct nouveau_gpuobj *dma = priv->vm->pgt[0].obj[0]; + struct nvkm_gpuobj *dma = priv->vm->pgt[0].obj[0]; int ret; - ret = nouveau_mmu_init(&priv->base); + ret = nvkm_mmu_init(&priv->base); if (ret) return ret; @@ -147,13 +145,13 @@ nv41_mmu_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass +struct nvkm_oclass nv41_mmu_oclass = { .handle = NV_SUBDEV(MMU, 0x41), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv41_mmu_ctor, .dtor = nv04_mmu_dtor, .init = nv41_mmu_init, - .fini = _nouveau_mmu_fini, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c index f5319e3..b90ded1 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.c @@ -21,14 +21,12 @@ * * Authors: Ben Skeggs */ +#include "nv04.h" +#include #include #include - #include -#include - -#include "nv04.h" #define NV44_GART_SIZE (512 * 1024 * 1024) #define NV44_GART_PAGE ( 4 * 1024) @@ -38,7 +36,7 @@ ******************************************************************************/ static void -nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, +nv44_vm_fill(struct nvkm_gpuobj *pgt, dma_addr_t null, dma_addr_t *list, u32 pte, u32 cnt) { u32 base = (pte << 2) & ~0x0000000f; @@ -84,8 +82,8 @@ nv44_vm_fill(struct nouveau_gpuobj *pgt, dma_addr_t null, } static void -nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv44_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { struct nv04_mmu_priv *priv = (void *)vma->vm->mmu; u32 tmp[4]; @@ -115,9 +113,9 @@ nv44_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv44_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { - struct nv04_mmu_priv *priv = (void *)nouveau_mmu(pgt); + struct nv04_mmu_priv *priv = (void *)nvkm_mmu(pgt); if (pte & 3) { u32 max = 4 - (pte & 3); @@ -140,7 +138,7 @@ nv44_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv44_vm_flush(struct nouveau_vm *vm) +nv44_vm_flush(struct nvkm_vm *vm) { struct nv04_mmu_priv *priv = (void *)vm->mmu; nv_wr32(priv, 0x100814, priv->base.limit - NV44_GART_PAGE); @@ -155,22 +153,22 @@ nv44_vm_flush(struct nouveau_vm *vm) ******************************************************************************/ static int -nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv44_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { - struct nouveau_device *device = nv_device(parent); + struct nvkm_device *device = nv_device(parent); struct nv04_mmu_priv *priv; int ret; if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) || - !nouveau_boolopt(device->cfgopt, "NvPCIE", true)) { - return nouveau_object_ctor(parent, engine, &nv04_mmu_oclass, - data, size, pobject); + !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) { + return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass, + data, size, pobject); } - ret = nouveau_mmu_create(parent, engine, oclass, "PCIEGART", - "pciegart", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART", + "pciegart", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -191,15 +189,15 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return -ENOMEM; } - ret = nouveau_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, - &priv->vm); + ret = nvkm_vm_create(&priv->base, 0, NV44_GART_SIZE, 0, 4096, + &priv->vm); if (ret) return ret; - ret = nouveau_gpuobj_new(nv_object(priv), NULL, - (NV44_GART_SIZE / NV44_GART_PAGE) * 4, - 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, - &priv->vm->pgt[0].obj[0]); + ret = nvkm_gpuobj_new(nv_object(priv), NULL, + (NV44_GART_SIZE / NV44_GART_PAGE) * 4, + 512 * 1024, NVOBJ_FLAG_ZERO_ALLOC, + &priv->vm->pgt[0].obj[0]); priv->vm->pgt[0].refcount[0] = 1; if (ret) return ret; @@ -208,14 +206,14 @@ nv44_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, } static int -nv44_mmu_init(struct nouveau_object *object) +nv44_mmu_init(struct nvkm_object *object) { struct nv04_mmu_priv *priv = (void *)object; - struct nouveau_gpuobj *gart = priv->vm->pgt[0].obj[0]; + struct nvkm_gpuobj *gart = priv->vm->pgt[0].obj[0]; u32 addr; int ret; - ret = nouveau_mmu_init(&priv->base); + ret = nvkm_mmu_init(&priv->base); if (ret) return ret; @@ -237,13 +235,13 @@ nv44_mmu_init(struct nouveau_object *object) return 0; } -struct nouveau_oclass +struct nvkm_oclass nv44_mmu_oclass = { .handle = NV_SUBDEV(MMU, 0x44), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv44_mmu_ctor, .dtor = nv04_mmu_dtor, .init = nv44_mmu_init, - .fini = _nouveau_mmu_fini, + .fini = _nvkm_mmu_fini, }, }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c index 70e1a14..b83550f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c @@ -21,22 +21,20 @@ * * Authors: Ben Skeggs */ +#include +#include +#include +#include -#include +#include #include -#include -#include -#include -#include - struct nv50_mmu_priv { - struct nouveau_mmu base; + struct nvkm_mmu base; }; static void -nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, - struct nouveau_gpuobj *pgt[2]) +nv50_vm_map_pgt(struct nvkm_gpuobj *pgd, u32 pde, struct nvkm_gpuobj *pgt[2]) { u64 phys = 0xdeadcafe00000000ULL; u32 coverage = 0; @@ -64,7 +62,7 @@ nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, } static inline u64 -vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) +vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target) { phys |= 1; /* present */ phys |= (u64)memtype << 40; @@ -77,8 +75,8 @@ vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) } static void -nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) +nv50_vm_map(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) { u32 comp = (mem->memtype & 0x180) >> 7; u32 block, target; @@ -86,8 +84,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, /* IGPs don't have real VRAM, re-target to stolen system memory */ target = 0; - if (nouveau_fb(vma->vm->mmu)->ram->stolen) { - phys += nouveau_fb(vma->vm->mmu)->ram->stolen; + if (nvkm_fb(vma->vm->mmu)->ram->stolen) { + phys += nvkm_fb(vma->vm->mmu)->ram->stolen; target = 3; } @@ -124,8 +122,8 @@ nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, - struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) +nv50_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt, + struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) { u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; pte <<= 3; @@ -138,7 +136,7 @@ nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, } static void -nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) +nv50_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt) { pte <<= 3; while (cnt--) { @@ -149,11 +147,11 @@ nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) } static void -nv50_vm_flush(struct nouveau_vm *vm) +nv50_vm_flush(struct nvkm_vm *vm) { struct nv50_mmu_priv *priv = (void *)vm->mmu; - struct nouveau_bar *bar = nouveau_bar(priv); - struct nouveau_engine *engine; + struct nvkm_bar *bar = nvkm_bar(priv); + struct nvkm_engine *engine; int i, vme; bar->flush(bar); @@ -164,7 +162,7 @@ nv50_vm_flush(struct nouveau_vm *vm) continue; /* unfortunate hw bug workaround... */ - engine = nouveau_engine(priv, i); + engine = nvkm_engine(priv, i); if (engine && engine->tlb_flush) { engine->tlb_flush(engine); continue; @@ -194,25 +192,25 @@ nv50_vm_flush(struct nouveau_vm *vm) } static int -nv50_vm_create(struct nouveau_mmu *mmu, u64 offset, u64 length, - u64 mm_offset, struct nouveau_vm **pvm) +nv50_vm_create(struct nvkm_mmu *mmu, u64 offset, u64 length, + u64 mm_offset, struct nvkm_vm **pvm) { u32 block = (1 << (mmu->pgt_bits + 12)); if (block > length) block = length; - return nouveau_vm_create(mmu, offset, length, mm_offset, block, pvm); + return nvkm_vm_create(mmu, offset, length, mm_offset, block, pvm); } static int -nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, - struct nouveau_oclass *oclass, void *data, u32 size, - struct nouveau_object **pobject) +nv50_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine, + struct nvkm_oclass *oclass, void *data, u32 size, + struct nvkm_object **pobject) { struct nv50_mmu_priv *priv; int ret; - ret = nouveau_mmu_create(parent, engine, oclass, "VM", "vm", &priv); + ret = nvkm_mmu_create(parent, engine, oclass, "VM", "vm", &priv); *pobject = nv_object(priv); if (ret) return ret; @@ -231,13 +229,13 @@ nv50_mmu_ctor(struct nouveau_object *parent, struct nouveau_object *engine, return 0; } -struct nouveau_oclass +struct nvkm_oclass nv50_mmu_oclass = { .handle = NV_SUBDEV(MMU, 0x50), - .ofuncs = &(struct nouveau_ofuncs) { + .ofuncs = &(struct nvkm_ofuncs) { .ctor = nv50_mmu_ctor, - .dtor = _nouveau_mmu_dtor, - .init = _nouveau_mmu_init, - .fini = _nouveau_mmu_fini, + .dtor = _nvkm_mmu_dtor, + .init = _nvkm_mmu_init, + .fini = _nvkm_mmu_fini, }, }; -- 2.7.4