From 4240841335045c689855cf7d2ca9196ab5e4accf Mon Sep 17 00:00:00 2001 From: segher Date: Sat, 4 May 2013 21:19:08 +0000 Subject: [PATCH] * config/rs6000/predicates.md (reg_or_add_cint_operand, reg_or_sub_cint_operand): Delete "HOST_BITS_PER_WIDE_INT == 32" case. (reg_or_logical_cint_operand, easy_fp_constant, logical_const_operand): Delete "CONST_DOUBLE" case. * config/rs6000/rs6000.c (num_insns_constant_wide): Delete "HOST_BITS_PER_WIDE_INT == 64" test. (num_insns_constant): Ditto. Delete CONST_DOUBLE DImode/VOIDmode case. (build_mask64_2_operands): Delete "HOST_BITS_PER_WIDE_INT >= 64" test. (rs6000_emit_set_const): Delete CONST_DOUBLE case. (rs6000_emit_set_long_const): Delete "HOST_BITS_PER_WIDE_INT >= 64" test. (includes_rldic_lshift_p, includes_rldicr_lshift_p): Delete CONST_DOUBLE DImode/VOIDmode case. (INT_P, INT_LOWPART): Delete CONST_DOUBLE case. (print_operand): Delete "HOST_BITS_PER_WIDE_INT == 32" case. Delete CONST_DOUBLE VOIDmode case. (output_toc): Delete "HOST_BITS_PER_WIDE_INT == 32" case. (rs6000_rtx_costs): Delete CONST_DOUBLE DImode/VOIDmode case. * config/rs6000/rs6000.md (iordi3, xordi3, splitter for these): Delete CONST_DOUBLE case. (splitters for mov FMOVE64 const_double): Delete "HOST_BITS_PER_WIDE_INT == 32" case. Delete "HOST_BITS_PER_WIDE_INT >= 64" test. (splitter for mov DI const_int): Delete "HOST_BITS_PER_WIDE_INT == 32" case. (mov DI const_double): Delete. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@198601 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 30 ++++++ gcc/config/rs6000/predicates.md | 49 ++-------- gcc/config/rs6000/rs6000.c | 207 +++------------------------------------- gcc/config/rs6000/rs6000.md | 77 ++------------- 4 files changed, 63 insertions(+), 300 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a56d77..8db037d 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,33 @@ +2013-05-04 Segher Boessenkool + + * config/rs6000/predicates.md (reg_or_add_cint_operand, + reg_or_sub_cint_operand): Delete "HOST_BITS_PER_WIDE_INT == 32" case. + (reg_or_logical_cint_operand, easy_fp_constant, + logical_const_operand): Delete "CONST_DOUBLE" case. + * config/rs6000/rs6000.c (num_insns_constant_wide): Delete + "HOST_BITS_PER_WIDE_INT == 64" test. + (num_insns_constant): Ditto. Delete CONST_DOUBLE DImode/VOIDmode + case. + (build_mask64_2_operands): Delete "HOST_BITS_PER_WIDE_INT >= 64" test. + (rs6000_emit_set_const): Delete CONST_DOUBLE case. + (rs6000_emit_set_long_const): Delete "HOST_BITS_PER_WIDE_INT >= 64" + test. + (includes_rldic_lshift_p, includes_rldicr_lshift_p): Delete + CONST_DOUBLE DImode/VOIDmode case. + (INT_P, INT_LOWPART): Delete CONST_DOUBLE case. + (print_operand): Delete "HOST_BITS_PER_WIDE_INT == 32" case. Delete + CONST_DOUBLE VOIDmode case. + (output_toc): Delete "HOST_BITS_PER_WIDE_INT == 32" case. + (rs6000_rtx_costs): Delete CONST_DOUBLE DImode/VOIDmode case. + * config/rs6000/rs6000.md (iordi3, xordi3, splitter for these): + Delete CONST_DOUBLE case. + (splitters for mov FMOVE64 const_double): Delete + "HOST_BITS_PER_WIDE_INT == 32" case. Delete + "HOST_BITS_PER_WIDE_INT >= 64" test. + (splitter for mov DI const_int): Delete "HOST_BITS_PER_WIDE_INT == 32" + case. + (mov DI const_double): Delete. + 2013-05-04 Jakub Jelinek * combine.c (combine_simplify_rtx) : If nonzero_bits diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 8112f26..78ec1b2 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -279,22 +279,17 @@ ;; or non-special register. (define_predicate "reg_or_add_cint_operand" (if_then_else (match_code "const_int") - (match_test "(HOST_BITS_PER_WIDE_INT == 32 - && (mode == SImode || INTVAL (op) < 0x7fff8000)) - || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) - < (unsigned HOST_WIDE_INT) 0x100000000ll)") + (match_test "(unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) + < (unsigned HOST_WIDE_INT) 0x100000000ll") (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if op is a constant integer valid for subtraction ;; or non-special register. (define_predicate "reg_or_sub_cint_operand" (if_then_else (match_code "const_int") - (match_test "(HOST_BITS_PER_WIDE_INT == 32 - && (mode == SImode || - INTVAL (op) < 0x7fff8000)) - || ((unsigned HOST_WIDE_INT) (- INTVAL (op) - + (mode == SImode - ? 0x80000000 : 0x80008000)) - < (unsigned HOST_WIDE_INT) 0x100000000ll)") + (match_test "(unsigned HOST_WIDE_INT) + (- INTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000)) + < (unsigned HOST_WIDE_INT) 0x100000000ll") (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if op is any 32-bit unsigned constant integer @@ -305,11 +300,7 @@ && INTVAL (op) >= 0) || ((INTVAL (op) & GET_MODE_MASK (mode) & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)") - (if_then_else (match_code "const_double") - (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT - && mode == DImode - && CONST_DOUBLE_HIGH (op) == 0") - (match_operand 0 "gpc_reg_operand")))) + (match_operand 0 "gpc_reg_operand"))) ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register ;; with no more than one instruction per word. @@ -403,9 +394,7 @@ return num_insns_constant_wide (k[0]) == 1; case DImode: - return ((TARGET_POWERPC64 - && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0) - || (num_insns_constant (op, DImode) <= 2)); + return (num_insns_constant (op, DImode) <= 2); case SImode: return 1; @@ -605,29 +594,11 @@ ;; Return 1 if the operand is a constant that can be used as the operand ;; of an OR or XOR. (define_predicate "logical_const_operand" - (match_code "const_int,const_double") + (match_code "const_int") { - HOST_WIDE_INT opl, oph; - - if (GET_CODE (op) == CONST_INT) - { - opl = INTVAL (op) & GET_MODE_MASK (mode); - - if (HOST_BITS_PER_WIDE_INT <= 32 - && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0) - return 0; - } - else if (GET_CODE (op) == CONST_DOUBLE) - { - gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT); + HOST_WIDE_INT opl; - opl = CONST_DOUBLE_LOW (op); - oph = CONST_DOUBLE_HIGH (op); - if (oph != 0) - return 0; - } - else - return 0; + opl = INTVAL (op) & GET_MODE_MASK (mode); return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4f7fc70..28f3160 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -4258,7 +4258,6 @@ num_insns_constant_wide (HOST_WIDE_INT value) && (value >> 31 == -1 || value >> 31 == 0)) return 1; -#if HOST_BITS_PER_WIDE_INT == 64 else if (TARGET_POWERPC64) { HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; @@ -4277,7 +4276,6 @@ num_insns_constant_wide (HOST_WIDE_INT value) return (num_insns_constant_wide (high) + num_insns_constant_wide (low) + 1); } -#endif else return 2; @@ -4291,12 +4289,10 @@ num_insns_constant (rtx op, enum machine_mode mode) switch (GET_CODE (op)) { case CONST_INT: -#if HOST_BITS_PER_WIDE_INT == 64 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1 && mask64_operand (op, mode)) return 2; else -#endif return num_insns_constant_wide (INTVAL (op)); case CONST_DOUBLE: @@ -4313,24 +4309,16 @@ num_insns_constant (rtx op, enum machine_mode mode) return num_insns_constant_wide ((HOST_WIDE_INT) l); } - if (mode == VOIDmode || mode == DImode) - { - high = CONST_DOUBLE_HIGH (op); - low = CONST_DOUBLE_LOW (op); - } - else - { - long l[2]; - REAL_VALUE_TYPE rv; + long l[2]; + REAL_VALUE_TYPE rv; - REAL_VALUE_FROM_CONST_DOUBLE (rv, op); - if (DECIMAL_FLOAT_MODE_P (mode)) - REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); - else - REAL_VALUE_TO_TARGET_DOUBLE (rv, l); - high = l[WORDS_BIG_ENDIAN == 0]; - low = l[WORDS_BIG_ENDIAN != 0]; - } + REAL_VALUE_FROM_CONST_DOUBLE (rv, op); + if (DECIMAL_FLOAT_MODE_P (mode)) + REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l); + else + REAL_VALUE_TO_TARGET_DOUBLE (rv, l); + high = l[WORDS_BIG_ENDIAN == 0]; + low = l[WORDS_BIG_ENDIAN != 0]; if (TARGET_32BIT) return (num_insns_constant_wide (low) @@ -5031,7 +5019,6 @@ rs6000_expand_vector_extract (rtx target, rtx vec, int elt) void build_mask64_2_operands (rtx in, rtx *out) { -#if HOST_BITS_PER_WIDE_INT >= 64 unsigned HOST_WIDE_INT c, lsb, m1, m2; int shift; @@ -5088,11 +5075,6 @@ build_mask64_2_operands (rtx in, rtx *out) out[1] = GEN_INT (m1); out[2] = GEN_INT (shift); out[3] = GEN_INT (m2); -#else - (void)in; - (void)out; - gcc_unreachable (); -#endif } /* Return TRUE if OP is an invalid SUBREG operation on the e500. */ @@ -7051,16 +7033,6 @@ rs6000_emit_set_const (rtx dest, enum machine_mode mode, c1 = -(c0 < 0); break; - case CONST_DOUBLE: -#if HOST_BITS_PER_WIDE_INT >= 64 - c0 = CONST_DOUBLE_LOW (source); - c1 = -(c0 < 0); -#else - c0 = CONST_DOUBLE_LOW (source); - c1 = CONST_DOUBLE_HIGH (source); -#endif - break; - default: gcc_unreachable (); } @@ -7104,9 +7076,7 @@ rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2) ud1 = c1 & 0xffff; ud2 = (c1 & 0xffff0000) >> 16; -#if HOST_BITS_PER_WIDE_INT >= 64 c2 = c1 >> 32; -#endif ud3 = c2 & 0xffff; ud4 = (c2 & 0xffff0000) >> 16; @@ -13560,60 +13530,6 @@ includes_rldic_lshift_p (rtx shiftop, rtx andop) lsb = c & -c; return c == -lsb; } - else if (GET_CODE (andop) == CONST_DOUBLE - && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) - { - HOST_WIDE_INT low, high, lsb; - HOST_WIDE_INT shift_mask_low, shift_mask_high; - - low = CONST_DOUBLE_LOW (andop); - if (HOST_BITS_PER_WIDE_INT < 64) - high = CONST_DOUBLE_HIGH (andop); - - if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0)) - || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0))) - return 0; - - if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) - { - shift_mask_high = ~0; - if (INTVAL (shiftop) > 32) - shift_mask_high <<= INTVAL (shiftop) - 32; - - lsb = high & -high; - - if (-lsb != shift_mask_high || INTVAL (shiftop) < 32) - return 0; - - high = ~high; - high &= -lsb; - - lsb = high & -high; - return high == -lsb; - } - - shift_mask_low = ~0; - shift_mask_low <<= INTVAL (shiftop); - - lsb = low & -low; - - if (-lsb != shift_mask_low) - return 0; - - if (HOST_BITS_PER_WIDE_INT < 64) - high = ~high; - low = ~low; - low &= -lsb; - - if (HOST_BITS_PER_WIDE_INT < 64 && low == 0) - { - lsb = high & -high; - return high == -lsb; - } - - lsb = low & -low; - return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); - } else return 0; } @@ -13644,46 +13560,6 @@ includes_rldicr_lshift_p (rtx shiftop, rtx andop) /* Check we have all 1's above the transition, and reject all 1's. */ return c == -lsb && lsb != 1; } - else if (GET_CODE (andop) == CONST_DOUBLE - && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode)) - { - HOST_WIDE_INT low, lsb, shift_mask_low; - - low = CONST_DOUBLE_LOW (andop); - - if (HOST_BITS_PER_WIDE_INT < 64) - { - HOST_WIDE_INT high, shift_mask_high; - - high = CONST_DOUBLE_HIGH (andop); - - if (low == 0) - { - shift_mask_high = ~0; - if (INTVAL (shiftop) > 32) - shift_mask_high <<= INTVAL (shiftop) - 32; - - lsb = high & -high; - - if ((lsb & shift_mask_high) == 0) - return 0; - - return high == -lsb; - } - if (high != ~0) - return 0; - } - - shift_mask_low = ~0; - shift_mask_low <<= INTVAL (shiftop); - - lsb = low & -low; - - if ((lsb & shift_mask_low) == 0) - return 0; - - return low == -lsb && lsb != 1; - } else return 0; } @@ -14977,11 +14853,9 @@ rs6000_init_machine_status (void) /* These macros test for integers and extract the low-order bits. */ #define INT_P(X) \ -((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ - && GET_MODE (X) == VOIDmode) +(GET_CODE (X) == CONST_INT && GET_MODE (X) == VOIDmode) -#define INT_LOWPART(X) \ - (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) +#define INT_LOWPART(X) INTVAL (X) int extract_MB (rtx op) @@ -15544,15 +15418,7 @@ print_operand (FILE *file, rtx x, int code) case 'W': /* MB value for a PowerPC64 rldic operand. */ - i = clz_hwi (GET_CODE (x) == CONST_INT - ? INTVAL (x) : CONST_DOUBLE_HIGH (x)); - -#if HOST_BITS_PER_WIDE_INT == 32 - if (GET_CODE (x) == CONST_INT && i > 0) - i += 32; /* zero-extend high-part was all 0's */ - else if (GET_CODE (x) == CONST_DOUBLE && i == 32) - i = clz_hwi (CONST_DOUBLE_LOW (x)) + 32; -#endif + i = clz_hwi (INTVAL (x)); fprintf (file, "%d", i); return; @@ -22511,29 +22377,13 @@ output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) return; } } - else if (GET_MODE (x) == VOIDmode - && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)) + else if (GET_MODE (x) == VOIDmode && GET_CODE (x) == CONST_INT) { unsigned HOST_WIDE_INT low; HOST_WIDE_INT high; - if (GET_CODE (x) == CONST_DOUBLE) - { - low = CONST_DOUBLE_LOW (x); - high = CONST_DOUBLE_HIGH (x); - } - else -#if HOST_BITS_PER_WIDE_INT == 32 - { - low = INTVAL (x); - high = (low & 0x80000000) ? ~0 : 0; - } -#else - { - low = INTVAL (x) & 0xffffffff; - high = (HOST_WIDE_INT) INTVAL (x) >> 32; - } -#endif + low = INTVAL (x) & 0xffffffff; + high = (HOST_WIDE_INT) INTVAL (x) >> 32; /* TOC entries are always Pmode-sized, so when big-endian smaller integer constants in the TOC need to be padded. @@ -22549,15 +22399,10 @@ output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode) if (WORDS_BIG_ENDIAN && POINTER_SIZE > GET_MODE_BITSIZE (mode)) { -#if HOST_BITS_PER_WIDE_INT == 32 - lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode), - POINTER_SIZE, &low, &high, 0); -#else low |= high << 32; low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode); high = (HOST_WIDE_INT) low >> 32; low &= 0xffffffff; -#endif } if (TARGET_64BIT) @@ -26352,28 +26197,6 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, /* FALLTHRU */ case CONST_DOUBLE: - if (mode == DImode && code == CONST_DOUBLE) - { - if ((outer_code == IOR || outer_code == XOR) - && CONST_DOUBLE_HIGH (x) == 0 - && (CONST_DOUBLE_LOW (x) - & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0) - { - *total = 0; - return true; - } - else if ((outer_code == AND && and64_2_operand (x, DImode)) - || ((outer_code == SET - || outer_code == IOR - || outer_code == XOR) - && CONST_DOUBLE_HIGH (x) == 0)) - { - *total = COSTS_N_INSNS (1); - return true; - } - } - /* FALLTHRU */ - case CONST: case HIGH: case SYMBOL_REF: diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index bae804a..bdf19f8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8018,20 +8018,9 @@ || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (DImode)); - if (GET_CODE (operands[2]) == CONST_INT) - { - value = INTVAL (operands[2]); - emit_insn (gen_iordi3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); - } - else - { - value = CONST_DOUBLE_LOW (operands[2]); - emit_insn (gen_iordi3 (tmp, operands[1], - immed_double_const (value - & (~ (HOST_WIDE_INT) 0xffff), - 0, DImode))); - } + value = INTVAL (operands[2]); + emit_insn (gen_iordi3 (tmp, operands[1], + GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; @@ -8052,20 +8041,9 @@ || rtx_equal_p (operands[0], operands[1])) ? operands[0] : gen_reg_rtx (DImode)); - if (GET_CODE (operands[2]) == CONST_INT) - { - value = INTVAL (operands[2]); - emit_insn (gen_xordi3 (tmp, operands[1], - GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); - } - else - { - value = CONST_DOUBLE_LOW (operands[2]); - emit_insn (gen_xordi3 (tmp, operands[1], - immed_double_const (value - & (~ (HOST_WIDE_INT) 0xffff), - 0, DImode))); - } + value = INTVAL (operands[2]); + emit_insn (gen_xordi3 (tmp, operands[1], + GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); DONE; @@ -8156,19 +8134,8 @@ { rtx i3,i4; - if (GET_CODE (operands[2]) == CONST_DOUBLE) - { - HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); - i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), - 0, DImode); - i4 = GEN_INT (value & 0xffff); - } - else - { - i3 = GEN_INT (INTVAL (operands[2]) - & (~ (HOST_WIDE_INT) 0xffff)); - i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); - } + i3 = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); + i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, operands[1], i3); operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, @@ -8827,12 +8794,8 @@ operands[2] = operand_subword (operands[0], endian, 0, mode); operands[3] = operand_subword (operands[0], 1 - endian, 0, mode); -#if HOST_BITS_PER_WIDE_INT == 32 - operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; -#else operands[4] = GEN_INT (value >> 32); operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); -#endif }") (define_split @@ -8874,23 +8837,17 @@ int endian = (WORDS_BIG_ENDIAN == 0); long l[2]; REAL_VALUE_TYPE rv; -#if HOST_BITS_PER_WIDE_INT >= 64 HOST_WIDE_INT val; -#endif REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); (rv, l); operands[2] = gen_lowpart (DImode, operands[0]); /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ -#if HOST_BITS_PER_WIDE_INT >= 64 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); operands[3] = gen_int_mode (val, DImode); -#else - operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); -#endif }") ;; Don't have reload use general registers to load a constant. It is @@ -9508,12 +9465,8 @@ DImode); operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, DImode); -#if HOST_BITS_PER_WIDE_INT == 32 - operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; -#else operands[4] = GEN_INT (value >> 32); operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); -#endif }") (define_split @@ -9600,20 +9553,6 @@ (const_string "mffgpr")]) (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4,4")]) -;; immediate value valid for a single instruction hiding in a const_double -(define_insn "" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (match_operand:DI 1 "const_double_operand" "F"))] - "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 - && GET_CODE (operands[1]) == CONST_DOUBLE - && num_insns_constant (operands[1], DImode) == 1" - "* -{ - return ((unsigned HOST_WIDE_INT) - (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) - ? \"li %0,%1\" : \"lis %0,%v1\"; -}") - ;; Generate all one-bits and clear left or right. ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. (define_split -- 2.7.4