From 419948fe6708021524f86e15d755719d634ab8d2 Mon Sep 17 00:00:00 2001 From: Yeting Kuo Date: Wed, 22 Feb 2023 14:50:11 +0800 Subject: [PATCH] [VP] Reorder is_int_min_poison/is_zero_poison operand before mask for vp.abs/ctlz/cttz. The patch ensures last two operands of vp.abs/ctlz/cttz are mask and evl. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D144536 --- llvm/include/llvm/IR/Intrinsics.td | 14 +- llvm/include/llvm/IR/VPIntrinsics.def | 14 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 10 +- .../test/Analysis/CostModel/RISCV/int-bit-manip.ll | 548 ++++++++++----------- llvm/test/CodeGen/RISCV/rvv/abs-vp.ll | 144 +++--- llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 240 ++++----- llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll | 240 ++++----- .../test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll | 111 +++-- .../CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll | 180 +++---- .../CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll | 180 +++---- llvm/unittests/IR/VPIntrinsicTest.cpp | 6 +- 11 files changed, 843 insertions(+), 844 deletions(-) diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index 34b9f2c..ee5ecf2 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -1545,9 +1545,9 @@ let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in { llvm_i32_ty]>; def int_vp_abs : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], [ LLVMMatchType<0>, + llvm_i1_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, - llvm_i32_ty, - llvm_i1_ty]>; + llvm_i32_ty]>; def int_vp_smin : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], [ LLVMMatchType<0>, LLVMMatchType<0>, @@ -1826,17 +1826,17 @@ let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn] in { llvm_i32_ty]>; } -let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn, ImmArg>] in { +let IntrProperties = [IntrNoMem, IntrNoSync, IntrWillReturn, ImmArg>] in { def int_vp_ctlz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], [ LLVMMatchType<0>, + llvm_i1_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, - llvm_i32_ty, - llvm_i1_ty]>; + llvm_i32_ty]>; def int_vp_cttz : DefaultAttrsIntrinsic<[ llvm_anyvector_ty ], [ LLVMMatchType<0>, + llvm_i1_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, - llvm_i32_ty, - llvm_i1_ty]>; + llvm_i32_ty]>; } def int_get_active_lane_mask: diff --git a/llvm/include/llvm/IR/VPIntrinsics.def b/llvm/include/llvm/IR/VPIntrinsics.def index 359f178..85ca1ee 100644 --- a/llvm/include/llvm/IR/VPIntrinsics.def +++ b/llvm/include/llvm/IR/VPIntrinsics.def @@ -222,8 +222,10 @@ BEGIN_REGISTER_VP(vp_umax, 2, 3, VP_UMAX, -1) VP_PROPERTY_BINARYOP END_REGISTER_VP(vp_umax, VP_UMAX) -// llvm.vp.abs(x,mask,vlen,is_int_min_poison) -BEGIN_REGISTER_VP(vp_abs, 1, 2, VP_ABS, -1) +// llvm.vp.abs(x,is_int_min_poison,mask,vlen) +BEGIN_REGISTER_VP_INTRINSIC(vp_abs, 2, 3) +BEGIN_REGISTER_VP_SDNODE(VP_ABS, -1, vp_abs, 1, 2) +HELPER_MAP_VPID_TO_VPSD(vp_abs, VP_ABS) END_REGISTER_VP(vp_abs, VP_ABS) // llvm.vp.bswap(x,mask,vlen) @@ -238,16 +240,16 @@ END_REGISTER_VP(vp_bitreverse, VP_BITREVERSE) BEGIN_REGISTER_VP(vp_ctpop, 1, 2, VP_CTPOP, -1) END_REGISTER_VP(vp_ctpop, VP_CTPOP) -// llvm.vp.ctlz(x,mask,vlen, is_zero_poison) -BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 1, 2) +// llvm.vp.ctlz(x,is_zero_poison,mask,vlen) +BEGIN_REGISTER_VP_INTRINSIC(vp_ctlz, 2, 3) BEGIN_REGISTER_VP_SDNODE(VP_CTLZ, -1, vp_ctlz, 1, 2) END_REGISTER_VP_SDNODE(VP_CTLZ) BEGIN_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF, -1, vp_ctlz_zero_undef, 1, 2) END_REGISTER_VP_SDNODE(VP_CTLZ_ZERO_UNDEF) END_REGISTER_VP_INTRINSIC(vp_ctlz) -// llvm.vp.cttz(x,mask,vlen, is_zero_poison) -BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 1, 2) +// llvm.vp.cttz(x,is_zero_poison,mask,vlen) +BEGIN_REGISTER_VP_INTRINSIC(vp_cttz, 2, 3) BEGIN_REGISTER_VP_SDNODE(VP_CTTZ, -1, vp_cttz, 1, 2) END_REGISTER_VP_SDNODE(VP_CTTZ) BEGIN_REGISTER_VP_SDNODE(VP_CTTZ_ZERO_UNDEF, -1, vp_cttz_zero_undef, 1, 2) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 650bb536..9d5db58 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7446,12 +7446,12 @@ static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin) { std::optional ResOPC; switch (VPIntrin.getIntrinsicID()) { case Intrinsic::vp_ctlz: { - bool IsZeroUndef = cast(VPIntrin.getArgOperand(3))->isOne(); + bool IsZeroUndef = cast(VPIntrin.getArgOperand(1))->isOne(); ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ; break; } case Intrinsic::vp_cttz: { - bool IsZeroUndef = cast(VPIntrin.getArgOperand(3))->isOne(); + bool IsZeroUndef = cast(VPIntrin.getArgOperand(1))->isOne(); ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ; break; } @@ -7794,10 +7794,8 @@ void SelectionDAGBuilder::visitVectorPredicationIntrinsic( case ISD::VP_CTLZ_ZERO_UNDEF: case ISD::VP_CTTZ: case ISD::VP_CTTZ_ZERO_UNDEF: { - // Pop is_zero_poison operand for cp.ctlz/cttz or - // is_int_min_poison operand for vp.abs. - OpValues.pop_back(); - SDValue Result = DAG.getNode(Opcode, DL, VTs, OpValues); + SDValue Result = + DAG.getNode(Opcode, DL, VTs, {OpValues[0], OpValues[2], OpValues[3]}); setValue(&VPIntrin, Result); break; } diff --git a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll index 1d82c27..393e924 100644 --- a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll +++ b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll @@ -384,211 +384,211 @@ define void @vp_ctpop() { define void @vp_ctlz() { ; CHECK-LABEL: 'vp_ctlz' -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %1 = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %2 = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %3 = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %4 = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %5 = call @llvm.vp.ctlz.nxv1i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %6 = call @llvm.vp.ctlz.nxv2i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %7 = call @llvm.vp.ctlz.nxv4i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %8 = call @llvm.vp.ctlz.nxv8i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %9 = call @llvm.vp.ctlz.nxv16i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %10 = call @llvm.vp.ctlz.nxv32i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %11 = call @llvm.vp.ctlz.nxv64i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %12 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %13 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %14 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %15 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %16 = call @llvm.vp.ctlz.nxv1i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %17 = call @llvm.vp.ctlz.nxv2i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %18 = call @llvm.vp.ctlz.nxv4i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %19 = call @llvm.vp.ctlz.nxv8i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %20 = call @llvm.vp.ctlz.nxv16i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %21 = call @llvm.vp.ctlz.nxv32i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %22 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %23 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %24 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %25 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %26 = call @llvm.vp.ctlz.nxv1i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %27 = call @llvm.vp.ctlz.nxv2i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %28 = call @llvm.vp.ctlz.nxv4i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %29 = call @llvm.vp.ctlz.nxv8i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %30 = call @llvm.vp.ctlz.nxv16i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %31 = call @llvm.vp.ctlz.nxv32i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %32 = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %33 = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %34 = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %35 = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %36 = call @llvm.vp.ctlz.nxv1i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %37 = call @llvm.vp.ctlz.nxv2i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %38 = call @llvm.vp.ctlz.nxv4i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %39 = call @llvm.vp.ctlz.nxv8i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %40 = call @llvm.vp.ctlz.nxv16i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %41 = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %42 = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %43 = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %44 = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %45 = call @llvm.vp.ctlz.nxv1i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %46 = call @llvm.vp.ctlz.nxv2i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %47 = call @llvm.vp.ctlz.nxv4i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %48 = call @llvm.vp.ctlz.nxv8i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %49 = call @llvm.vp.ctlz.nxv16i64( undef, undef, i32 undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %1 = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %2 = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %3 = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %4 = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %5 = call @llvm.vp.ctlz.nxv1i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %6 = call @llvm.vp.ctlz.nxv2i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %7 = call @llvm.vp.ctlz.nxv4i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %8 = call @llvm.vp.ctlz.nxv8i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %9 = call @llvm.vp.ctlz.nxv16i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %10 = call @llvm.vp.ctlz.nxv32i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %11 = call @llvm.vp.ctlz.nxv64i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %12 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %13 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %14 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %15 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %16 = call @llvm.vp.ctlz.nxv1i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %17 = call @llvm.vp.ctlz.nxv2i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %18 = call @llvm.vp.ctlz.nxv4i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %19 = call @llvm.vp.ctlz.nxv8i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %20 = call @llvm.vp.ctlz.nxv16i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %21 = call @llvm.vp.ctlz.nxv32i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %22 = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %23 = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %24 = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %25 = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %26 = call @llvm.vp.ctlz.nxv1i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %27 = call @llvm.vp.ctlz.nxv2i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %28 = call @llvm.vp.ctlz.nxv4i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %29 = call @llvm.vp.ctlz.nxv8i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %30 = call @llvm.vp.ctlz.nxv16i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %31 = call @llvm.vp.ctlz.nxv32i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %32 = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %33 = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %34 = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %35 = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %36 = call @llvm.vp.ctlz.nxv1i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %37 = call @llvm.vp.ctlz.nxv2i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %38 = call @llvm.vp.ctlz.nxv4i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %39 = call @llvm.vp.ctlz.nxv8i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %40 = call @llvm.vp.ctlz.nxv16i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %41 = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %42 = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %43 = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %44 = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %45 = call @llvm.vp.ctlz.nxv1i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %46 = call @llvm.vp.ctlz.nxv2i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %47 = call @llvm.vp.ctlz.nxv4i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 35 for instruction: %48 = call @llvm.vp.ctlz.nxv8i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 70 for instruction: %49 = call @llvm.vp.ctlz.nxv16i64( undef, i1 false, undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; - call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx1i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx2i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx4i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx8i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx16i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx32i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx64i8( undef, undef, i32 undef, i1 false) - call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx1i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx2i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx4i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx8i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx16i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx32i16( undef, undef, i32 undef, i1 false) - call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx1i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx2i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx4i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx8i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx16i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx32i16( undef, undef, i32 undef, i1 false) - call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx1i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx2i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx4i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx8i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx16i32( undef, undef, i32 undef, i1 false) - call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx1i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx2i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx4i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx8i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.ctlz.nvx16i64( undef, undef, i32 undef, i1 false) + call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.ctlz.nvx1i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx2i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx4i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx8i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx16i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx32i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx64i8( undef, i1 false, undef, i32 undef) + call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.ctlz.nvx1i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx2i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx4i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx8i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx16i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx32i16( undef, i1 false, undef, i32 undef) + call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.ctlz.nvx1i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx2i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx4i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx8i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx16i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx32i16( undef, i1 false, undef, i32 undef) + call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.ctlz.nvx1i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx2i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx4i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx8i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx16i32( undef, i1 false, undef, i32 undef) + call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.ctlz.nvx1i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx2i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx4i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx8i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.ctlz.nvx16i64( undef, i1 false, undef, i32 undef) ret void } define void @vp_cttz() { ; CHECK-LABEL: 'vp_cttz' -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %1 = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %2 = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %3 = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = call @llvm.vp.cttz.nxv1i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = call @llvm.vp.cttz.nxv2i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %7 = call @llvm.vp.cttz.nxv4i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %8 = call @llvm.vp.cttz.nxv8i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %9 = call @llvm.vp.cttz.nxv16i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %10 = call @llvm.vp.cttz.nxv32i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %11 = call @llvm.vp.cttz.nxv64i8( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %12 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %13 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %14 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %15 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %16 = call @llvm.vp.cttz.nxv1i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %17 = call @llvm.vp.cttz.nxv2i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %18 = call @llvm.vp.cttz.nxv4i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %19 = call @llvm.vp.cttz.nxv8i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %20 = call @llvm.vp.cttz.nxv16i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %21 = call @llvm.vp.cttz.nxv32i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %22 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %23 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %24 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %25 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %26 = call @llvm.vp.cttz.nxv1i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %27 = call @llvm.vp.cttz.nxv2i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %28 = call @llvm.vp.cttz.nxv4i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %29 = call @llvm.vp.cttz.nxv8i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %30 = call @llvm.vp.cttz.nxv16i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %31 = call @llvm.vp.cttz.nxv32i16( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %32 = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %33 = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %34 = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %35 = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %36 = call @llvm.vp.cttz.nxv1i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %37 = call @llvm.vp.cttz.nxv2i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %38 = call @llvm.vp.cttz.nxv4i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %39 = call @llvm.vp.cttz.nxv8i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %40 = call @llvm.vp.cttz.nxv16i32( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %41 = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %42 = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %43 = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %44 = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %45 = call @llvm.vp.cttz.nxv1i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %46 = call @llvm.vp.cttz.nxv2i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %47 = call @llvm.vp.cttz.nxv4i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %48 = call @llvm.vp.cttz.nxv8i64( undef, undef, i32 undef, i1 false) -; CHECK-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %49 = call @llvm.vp.cttz.nxv16i64( undef, undef, i32 undef, i1 false) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %1 = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %2 = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %3 = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %4 = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %5 = call @llvm.vp.cttz.nxv1i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %6 = call @llvm.vp.cttz.nxv2i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %7 = call @llvm.vp.cttz.nxv4i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %8 = call @llvm.vp.cttz.nxv8i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %9 = call @llvm.vp.cttz.nxv16i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %10 = call @llvm.vp.cttz.nxv32i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %11 = call @llvm.vp.cttz.nxv64i8( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %12 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %13 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %14 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %15 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %16 = call @llvm.vp.cttz.nxv1i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %17 = call @llvm.vp.cttz.nxv2i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %18 = call @llvm.vp.cttz.nxv4i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %19 = call @llvm.vp.cttz.nxv8i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %20 = call @llvm.vp.cttz.nxv16i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %21 = call @llvm.vp.cttz.nxv32i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %22 = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %23 = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %24 = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %25 = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %26 = call @llvm.vp.cttz.nxv1i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %27 = call @llvm.vp.cttz.nxv2i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %28 = call @llvm.vp.cttz.nxv4i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %29 = call @llvm.vp.cttz.nxv8i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %30 = call @llvm.vp.cttz.nxv16i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 23 for instruction: %31 = call @llvm.vp.cttz.nxv32i16( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %32 = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %33 = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %34 = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %35 = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %36 = call @llvm.vp.cttz.nxv1i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %37 = call @llvm.vp.cttz.nxv2i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %38 = call @llvm.vp.cttz.nxv4i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %39 = call @llvm.vp.cttz.nxv8i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %40 = call @llvm.vp.cttz.nxv16i32( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %41 = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %42 = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %43 = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %44 = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %45 = call @llvm.vp.cttz.nxv1i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %46 = call @llvm.vp.cttz.nxv2i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %47 = call @llvm.vp.cttz.nxv4i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 25 for instruction: %48 = call @llvm.vp.cttz.nxv8i64( undef, i1 false, undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %49 = call @llvm.vp.cttz.nxv16i64( undef, i1 false, undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; - call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx1i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx2i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx4i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx8i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx16i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx32i8( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx64i8( undef, undef, i32 undef, i1 false) - call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx1i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx2i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx4i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx8i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx16i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx32i16( undef, undef, i32 undef, i1 false) - call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx1i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx2i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx4i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx8i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx16i16( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx32i16( undef, undef, i32 undef, i1 false) - call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx1i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx2i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx4i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx8i32( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx16i32( undef, undef, i32 undef, i1 false) - call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, <2 x i1> undef, i32 undef, i1 false) - call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, <4 x i1> undef, i32 undef, i1 false) - call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, <8 x i1> undef, i32 undef, i1 false) - call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, <16 x i1> undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx1i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx2i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx4i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx8i64( undef, undef, i32 undef, i1 false) - call @llvm.vp.cttz.nvx16i64( undef, undef, i32 undef, i1 false) + call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.cttz.nvx1i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx2i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx4i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx8i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx16i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx32i8( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx64i8( undef, i1 false, undef, i32 undef) + call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.cttz.nvx1i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx2i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx4i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx8i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx16i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx32i16( undef, i1 false, undef, i32 undef) + call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.cttz.nvx1i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx2i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx4i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx8i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx16i16( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx32i16( undef, i1 false, undef, i32 undef) + call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.cttz.nvx1i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx2i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx4i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx8i32( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx16i32( undef, i1 false, undef, i32 undef) + call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> undef, i1 false, <2 x i1> undef, i32 undef) + call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> undef, i1 false, <4 x i1> undef, i32 undef) + call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> undef, i1 false, <8 x i1> undef, i32 undef) + call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> undef, i1 false, <16 x i1> undef, i32 undef) + call @llvm.vp.cttz.nvx1i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx2i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx4i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx8i64( undef, i1 false, undef, i32 undef) + call @llvm.vp.cttz.nvx16i64( undef, i1 false, undef, i32 undef) ret void } @@ -770,82 +770,82 @@ declare @llvm.vp.ctpop.nvx4i64(, @llvm.vp.ctpop.nvx8i64(, , i32) declare @llvm.vp.ctpop.nvx16i64(, , i32) -declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) -declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) -declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) -declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.ctlz.nvx1i8(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx2i8(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx4i8(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx8i8(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx16i8(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx32i8(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx64i8(, , i32, i1 immarg) -declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) -declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) -declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) -declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.ctlz.nvx1i16(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx2i16(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx4i16(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx8i16(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx16i16(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx32i16(, , i32, i1 immarg) -declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) -declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) -declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) -declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.ctlz.nvx1i32(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx2i32(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx4i32(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx8i32(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx16i32(, , i32, i1 immarg) -declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) -declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) -declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) -declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.ctlz.nvx1i64(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx2i64(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx4i64(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx8i64(, , i32, i1 immarg) -declare @llvm.vp.ctlz.nvx16i64(, , i32, i1 immarg) +declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32) +declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32) +declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32) +declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.ctlz.nvx1i8(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx2i8(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx4i8(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx8i8(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx16i8(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx32i8(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx64i8(, i1 immarg, , i32) +declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32) +declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32) +declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32) +declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.ctlz.nvx1i16(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx2i16(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx4i16(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx8i16(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx16i16(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx32i16(, i1 immarg, , i32) +declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32) +declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32) +declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32) +declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.ctlz.nvx1i32(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx2i32(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx4i32(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx8i32(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx16i32(, i1 immarg, , i32) +declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32) +declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32) +declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32) +declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.ctlz.nvx1i64(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx2i64(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx4i64(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx8i64(, i1 immarg, , i32) +declare @llvm.vp.ctlz.nvx16i64(, i1 immarg, , i32) -declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) -declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) -declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) -declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.cttz.nvx1i8(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx2i8(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx4i8(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx8i8(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx16i8(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx32i8(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx64i8(, , i32, i1 immarg) -declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) -declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) -declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) -declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.cttz.nvx1i16(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx2i16(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx4i16(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx8i16(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx16i16(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx32i16(, , i32, i1 immarg) -declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) -declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) -declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) -declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.cttz.nvx1i32(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx2i32(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx4i32(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx8i32(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx16i32(, , i32, i1 immarg) -declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) -declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) -declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) -declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) -declare @llvm.vp.cttz.nvx1i64(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx2i64(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx4i64(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx8i64(, , i32, i1 immarg) -declare @llvm.vp.cttz.nvx16i64(, , i32, i1 immarg) +declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32) +declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32) +declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32) +declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.cttz.nvx1i8(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx2i8(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx4i8(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx8i8(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx16i8(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx32i8(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx64i8(, i1 immarg, , i32) +declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32) +declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32) +declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32) +declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.cttz.nvx1i16(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx2i16(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx4i16(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx8i16(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx16i16(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx32i16(, i1 immarg, , i32) +declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32) +declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32) +declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32) +declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.cttz.nvx1i32(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx2i32(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx4i32(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx8i32(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx16i32(, i1 immarg, , i32) +declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32) +declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32) +declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32) +declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32) +declare @llvm.vp.cttz.nvx1i64(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx2i64(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx4i64(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx8i64(, i1 immarg, , i32) +declare @llvm.vp.cttz.nvx16i64(, i1 immarg, , i32) diff --git a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll index ab47baf..d5d755a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/abs-vp.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -declare @llvm.vp.abs.nxv1i8(, , i32, i1 immarg) +declare @llvm.vp.abs.nxv1i8(, i1 immarg, , i32) define @vp_abs_nxv1i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv1i8: @@ -13,7 +13,7 @@ define @vp_abs_nxv1i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call @llvm.vp.abs.nxv1i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -26,11 +26,11 @@ define @vp_abs_nxv1i8_unmasked( %va, i32 zero ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv2i8(, , i32, i1) +declare @llvm.vp.abs.nxv2i8(, i1 immarg, , i32) define @vp_abs_nxv2i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv2i8: @@ -39,7 +39,7 @@ define @vp_abs_nxv2i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call @llvm.vp.abs.nxv2i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -52,11 +52,11 @@ define @vp_abs_nxv2i8_unmasked( %va, i32 zero ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv4i8(, , i32, i1) +declare @llvm.vp.abs.nxv4i8(, i1 immarg, , i32) define @vp_abs_nxv4i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv4i8: @@ -65,7 +65,7 @@ define @vp_abs_nxv4i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call @llvm.vp.abs.nxv4i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -78,11 +78,11 @@ define @vp_abs_nxv4i8_unmasked( %va, i32 zero ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv8i8(, , i32, i1) +declare @llvm.vp.abs.nxv8i8(, i1 immarg, , i32) define @vp_abs_nxv8i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv8i8: @@ -91,7 +91,7 @@ define @vp_abs_nxv8i8( %va, ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call @llvm.vp.abs.nxv8i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -104,11 +104,11 @@ define @vp_abs_nxv8i8_unmasked( %va, i32 zero ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv16i8(, , i32, i1) +declare @llvm.vp.abs.nxv16i8(, i1 immarg, , i32) define @vp_abs_nxv16i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv16i8: @@ -117,7 +117,7 @@ define @vp_abs_nxv16i8( %va, @llvm.vp.abs.nxv16i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -130,11 +130,11 @@ define @vp_abs_nxv16i8_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv32i8(, , i32, i1) +declare @llvm.vp.abs.nxv32i8(, i1 immarg, , i32) define @vp_abs_nxv32i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv32i8: @@ -143,7 +143,7 @@ define @vp_abs_nxv32i8( %va, @llvm.vp.abs.nxv32i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv32i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -156,11 +156,11 @@ define @vp_abs_nxv32i8_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv32i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv32i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv64i8(, , i32, i1) +declare @llvm.vp.abs.nxv64i8(, i1 immarg, , i32) define @vp_abs_nxv64i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv64i8: @@ -169,7 +169,7 @@ define @vp_abs_nxv64i8( %va, @llvm.vp.abs.nxv64i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv64i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -182,11 +182,11 @@ define @vp_abs_nxv64i8_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv64i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv64i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv1i16(, , i32, i1) +declare @llvm.vp.abs.nxv1i16(, i1 immarg, , i32) define @vp_abs_nxv1i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv1i16: @@ -195,7 +195,7 @@ define @vp_abs_nxv1i16( %va, @llvm.vp.abs.nxv1i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -208,11 +208,11 @@ define @vp_abs_nxv1i16_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv2i16(, , i32, i1) +declare @llvm.vp.abs.nxv2i16(, i1 immarg, , i32) define @vp_abs_nxv2i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv2i16: @@ -221,7 +221,7 @@ define @vp_abs_nxv2i16( %va, @llvm.vp.abs.nxv2i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -234,11 +234,11 @@ define @vp_abs_nxv2i16_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv4i16(, , i32, i1) +declare @llvm.vp.abs.nxv4i16(, i1 immarg, , i32) define @vp_abs_nxv4i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv4i16: @@ -247,7 +247,7 @@ define @vp_abs_nxv4i16( %va, @llvm.vp.abs.nxv4i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -260,11 +260,11 @@ define @vp_abs_nxv4i16_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv8i16(, , i32, i1) +declare @llvm.vp.abs.nxv8i16(, i1 immarg, , i32) define @vp_abs_nxv8i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv8i16: @@ -273,7 +273,7 @@ define @vp_abs_nxv8i16( %va, @llvm.vp.abs.nxv8i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -286,11 +286,11 @@ define @vp_abs_nxv8i16_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv16i16(, , i32, i1) +declare @llvm.vp.abs.nxv16i16(, i1 immarg, , i32) define @vp_abs_nxv16i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv16i16: @@ -299,7 +299,7 @@ define @vp_abs_nxv16i16( %va, @llvm.vp.abs.nxv16i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -312,11 +312,11 @@ define @vp_abs_nxv16i16_unmasked( %va, i3 ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv32i16(, , i32, i1) +declare @llvm.vp.abs.nxv32i16(, i1 immarg, , i32) define @vp_abs_nxv32i16( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv32i16: @@ -325,7 +325,7 @@ define @vp_abs_nxv32i16( %va, @llvm.vp.abs.nxv32i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv32i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -338,11 +338,11 @@ define @vp_abs_nxv32i16_unmasked( %va, i3 ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv32i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv32i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv1i32(, , i32, i1) +declare @llvm.vp.abs.nxv1i32(, i1 immarg, , i32) define @vp_abs_nxv1i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv1i32: @@ -351,7 +351,7 @@ define @vp_abs_nxv1i32( %va, @llvm.vp.abs.nxv1i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -364,11 +364,11 @@ define @vp_abs_nxv1i32_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv2i32(, , i32, i1) +declare @llvm.vp.abs.nxv2i32(, i1 immarg, , i32) define @vp_abs_nxv2i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv2i32: @@ -377,7 +377,7 @@ define @vp_abs_nxv2i32( %va, @llvm.vp.abs.nxv2i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -390,11 +390,11 @@ define @vp_abs_nxv2i32_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv4i32(, , i32, i1) +declare @llvm.vp.abs.nxv4i32(, i1 immarg, , i32) define @vp_abs_nxv4i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv4i32: @@ -403,7 +403,7 @@ define @vp_abs_nxv4i32( %va, @llvm.vp.abs.nxv4i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -416,11 +416,11 @@ define @vp_abs_nxv4i32_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv8i32(, , i32, i1) +declare @llvm.vp.abs.nxv8i32(, i1 immarg, , i32) define @vp_abs_nxv8i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv8i32: @@ -429,7 +429,7 @@ define @vp_abs_nxv8i32( %va, @llvm.vp.abs.nxv8i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -442,11 +442,11 @@ define @vp_abs_nxv8i32_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv16i32(, , i32, i1) +declare @llvm.vp.abs.nxv16i32(, i1 immarg, , i32) define @vp_abs_nxv16i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv16i32: @@ -455,7 +455,7 @@ define @vp_abs_nxv16i32( %va, @llvm.vp.abs.nxv16i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -468,11 +468,11 @@ define @vp_abs_nxv16i32_unmasked( %va, i3 ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv1i64(, , i32, i1) +declare @llvm.vp.abs.nxv1i64(, i1 immarg, , i32) define @vp_abs_nxv1i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv1i64: @@ -481,7 +481,7 @@ define @vp_abs_nxv1i64( %va, @llvm.vp.abs.nxv1i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -494,11 +494,11 @@ define @vp_abs_nxv1i64_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv1i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv1i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv2i64(, , i32, i1) +declare @llvm.vp.abs.nxv2i64(, i1 immarg, , i32) define @vp_abs_nxv2i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv2i64: @@ -507,7 +507,7 @@ define @vp_abs_nxv2i64( %va, @llvm.vp.abs.nxv2i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -520,11 +520,11 @@ define @vp_abs_nxv2i64_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv2i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv2i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv4i64(, , i32, i1) +declare @llvm.vp.abs.nxv4i64(, i1 immarg, , i32) define @vp_abs_nxv4i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv4i64: @@ -533,7 +533,7 @@ define @vp_abs_nxv4i64( %va, @llvm.vp.abs.nxv4i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -546,11 +546,11 @@ define @vp_abs_nxv4i64_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv4i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv4i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv7i64(, , i32, i1) +declare @llvm.vp.abs.nxv7i64(, i1 immarg, , i32) define @vp_abs_nxv7i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv7i64: @@ -559,7 +559,7 @@ define @vp_abs_nxv7i64( %va, @llvm.vp.abs.nxv7i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv7i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -572,11 +572,11 @@ define @vp_abs_nxv7i64_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv7i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv7i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv8i64(, , i32, i1) +declare @llvm.vp.abs.nxv8i64(, i1 immarg, , i32) define @vp_abs_nxv8i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv8i64: @@ -585,7 +585,7 @@ define @vp_abs_nxv8i64( %va, @llvm.vp.abs.nxv8i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -598,11 +598,11 @@ define @vp_abs_nxv8i64_unmasked( %va, i32 z ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv8i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv8i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.abs.nxv16i64(, , i32, i1) +declare @llvm.vp.abs.nxv16i64(, i1 immarg, , i32) define @vp_abs_nxv16i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_nxv16i64: @@ -652,7 +652,7 @@ define @vp_abs_nxv16i64( %va, @llvm.vp.abs.nxv16i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -677,6 +677,6 @@ define @vp_abs_nxv16i64_unmasked( %va, i3 ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.abs.nxv16i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.abs.nxv16i64( %va, i1 false, %m, i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll index c42ea18..ffcd512 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -declare @llvm.vp.ctlz.nxv1i8(, , i32, i1 immarg) +declare @llvm.vp.ctlz.nxv1i8(, i1 immarg, , i32) define @vp_ctlz_nxv1i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv1i8: @@ -30,7 +30,7 @@ define @vp_ctlz_nxv1i8( %va, @llvm.vp.ctlz.nxv1i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -62,11 +62,11 @@ define @vp_ctlz_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv2i8(, , i32, i1) +declare @llvm.vp.ctlz.nxv2i8(, i1 immarg, , i32) define @vp_ctlz_nxv2i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv2i8: @@ -92,7 +92,7 @@ define @vp_ctlz_nxv2i8( %va, @llvm.vp.ctlz.nxv2i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -124,11 +124,11 @@ define @vp_ctlz_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv4i8(, , i32, i1) +declare @llvm.vp.ctlz.nxv4i8(, i1 immarg, , i32) define @vp_ctlz_nxv4i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv4i8: @@ -154,7 +154,7 @@ define @vp_ctlz_nxv4i8( %va, @llvm.vp.ctlz.nxv4i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -186,11 +186,11 @@ define @vp_ctlz_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv8i8(, , i32, i1) +declare @llvm.vp.ctlz.nxv8i8(, i1 immarg, , i32) define @vp_ctlz_nxv8i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv8i8: @@ -216,7 +216,7 @@ define @vp_ctlz_nxv8i8( %va, @llvm.vp.ctlz.nxv8i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -248,11 +248,11 @@ define @vp_ctlz_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv16i8(, , i32, i1) +declare @llvm.vp.ctlz.nxv16i8(, i1 immarg, , i32) define @vp_ctlz_nxv16i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv16i8: @@ -278,7 +278,7 @@ define @vp_ctlz_nxv16i8( %va, @llvm.vp.ctlz.nxv16i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -310,11 +310,11 @@ define @vp_ctlz_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv32i8(, , i32, i1) +declare @llvm.vp.ctlz.nxv32i8(, i1 immarg, , i32) define @vp_ctlz_nxv32i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv32i8: @@ -340,7 +340,7 @@ define @vp_ctlz_nxv32i8( %va, @llvm.vp.ctlz.nxv32i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -372,11 +372,11 @@ define @vp_ctlz_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv64i8(, , i32, i1) +declare @llvm.vp.ctlz.nxv64i8(, i1 immarg, , i32) define @vp_ctlz_nxv64i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv64i8: @@ -402,7 +402,7 @@ define @vp_ctlz_nxv64i8( %va, @llvm.vp.ctlz.nxv64i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -434,11 +434,11 @@ define @vp_ctlz_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv64i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv1i16(, , i32, i1) +declare @llvm.vp.ctlz.nxv1i16(, i1 immarg, , i32) define @vp_ctlz_nxv1i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv1i16: @@ -506,7 +506,7 @@ define @vp_ctlz_nxv1i16( %va, @llvm.vp.ctlz.nxv1i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -582,11 +582,11 @@ define @vp_ctlz_nxv1i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv2i16(, , i32, i1) +declare @llvm.vp.ctlz.nxv2i16(, i1 immarg, , i32) define @vp_ctlz_nxv2i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv2i16: @@ -654,7 +654,7 @@ define @vp_ctlz_nxv2i16( %va, @llvm.vp.ctlz.nxv2i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -730,11 +730,11 @@ define @vp_ctlz_nxv2i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv4i16(, , i32, i1) +declare @llvm.vp.ctlz.nxv4i16(, i1 immarg, , i32) define @vp_ctlz_nxv4i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv4i16: @@ -802,7 +802,7 @@ define @vp_ctlz_nxv4i16( %va, @llvm.vp.ctlz.nxv4i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -878,11 +878,11 @@ define @vp_ctlz_nxv4i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv8i16(, , i32, i1) +declare @llvm.vp.ctlz.nxv8i16(, i1 immarg, , i32) define @vp_ctlz_nxv8i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv8i16: @@ -950,7 +950,7 @@ define @vp_ctlz_nxv8i16( %va, @llvm.vp.ctlz.nxv8i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -1026,11 +1026,11 @@ define @vp_ctlz_nxv8i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv16i16(, , i32, i1) +declare @llvm.vp.ctlz.nxv16i16(, i1 immarg, , i32) define @vp_ctlz_nxv16i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv16i16: @@ -1098,7 +1098,7 @@ define @vp_ctlz_nxv16i16( %va, @llvm.vp.ctlz.nxv16i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -1174,11 +1174,11 @@ define @vp_ctlz_nxv16i16_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv32i16(, , i32, i1) +declare @llvm.vp.ctlz.nxv32i16(, i1 immarg, , i32) define @vp_ctlz_nxv32i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv32i16: @@ -1246,7 +1246,7 @@ define @vp_ctlz_nxv32i16( %va, @llvm.vp.ctlz.nxv32i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -1322,11 +1322,11 @@ define @vp_ctlz_nxv32i16_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv1i32(, , i32, i1) +declare @llvm.vp.ctlz.nxv1i32(, i1 immarg, , i32) define @vp_ctlz_nxv1i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv1i32: @@ -1400,7 +1400,7 @@ define @vp_ctlz_nxv1i32( %va, @llvm.vp.ctlz.nxv1i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1482,11 +1482,11 @@ define @vp_ctlz_nxv1i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv2i32(, , i32, i1) +declare @llvm.vp.ctlz.nxv2i32(, i1 immarg, , i32) define @vp_ctlz_nxv2i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv2i32: @@ -1560,7 +1560,7 @@ define @vp_ctlz_nxv2i32( %va, @llvm.vp.ctlz.nxv2i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1642,11 +1642,11 @@ define @vp_ctlz_nxv2i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv4i32(, , i32, i1) +declare @llvm.vp.ctlz.nxv4i32(, i1 immarg, , i32) define @vp_ctlz_nxv4i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv4i32: @@ -1720,7 +1720,7 @@ define @vp_ctlz_nxv4i32( %va, @llvm.vp.ctlz.nxv4i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1802,11 +1802,11 @@ define @vp_ctlz_nxv4i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv8i32(, , i32, i1) +declare @llvm.vp.ctlz.nxv8i32(, i1 immarg, , i32) define @vp_ctlz_nxv8i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv8i32: @@ -1880,7 +1880,7 @@ define @vp_ctlz_nxv8i32( %va, @llvm.vp.ctlz.nxv8i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1962,11 +1962,11 @@ define @vp_ctlz_nxv8i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv16i32(, , i32, i1) +declare @llvm.vp.ctlz.nxv16i32(, i1 immarg, , i32) define @vp_ctlz_nxv16i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv16i32: @@ -2040,7 +2040,7 @@ define @vp_ctlz_nxv16i32( %va, @llvm.vp.ctlz.nxv16i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -2122,11 +2122,11 @@ define @vp_ctlz_nxv16i32_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv1i64(, , i32, i1) +declare @llvm.vp.ctlz.nxv1i64(, i1 immarg, , i32) define @vp_ctlz_nxv1i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv1i64: @@ -2232,7 +2232,7 @@ define @vp_ctlz_nxv1i64( %va, @llvm.vp.ctlz.nxv1i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2346,11 +2346,11 @@ define @vp_ctlz_nxv1i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv2i64(, , i32, i1) +declare @llvm.vp.ctlz.nxv2i64(, i1 immarg, , i32) define @vp_ctlz_nxv2i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv2i64: @@ -2456,7 +2456,7 @@ define @vp_ctlz_nxv2i64( %va, @llvm.vp.ctlz.nxv2i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2570,11 +2570,11 @@ define @vp_ctlz_nxv2i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv4i64(, , i32, i1) +declare @llvm.vp.ctlz.nxv4i64(, i1 immarg, , i32) define @vp_ctlz_nxv4i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv4i64: @@ -2680,7 +2680,7 @@ define @vp_ctlz_nxv4i64( %va, @llvm.vp.ctlz.nxv4i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2794,11 +2794,11 @@ define @vp_ctlz_nxv4i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv7i64(, , i32, i1) +declare @llvm.vp.ctlz.nxv7i64(, i1 immarg, , i32) define @vp_ctlz_nxv7i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv7i64: @@ -2904,7 +2904,7 @@ define @vp_ctlz_nxv7i64( %va, @llvm.vp.ctlz.nxv7i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -3018,11 +3018,11 @@ define @vp_ctlz_nxv7i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv7i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv8i64(, , i32, i1) +declare @llvm.vp.ctlz.nxv8i64(, i1 immarg, , i32) define @vp_ctlz_nxv8i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv8i64: @@ -3128,7 +3128,7 @@ define @vp_ctlz_nxv8i64( %va, @llvm.vp.ctlz.nxv8i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -3242,11 +3242,11 @@ define @vp_ctlz_nxv8i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.ctlz.nxv16i64(, , i32, i1) +declare @llvm.vp.ctlz.nxv16i64(, i1 immarg, , i32) define @vp_ctlz_nxv16i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_nxv16i64: @@ -3571,7 +3571,7 @@ define @vp_ctlz_nxv16i64( %va, @llvm.vp.ctlz.nxv16i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -3855,7 +3855,7 @@ define @vp_ctlz_nxv16i64_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -3883,7 +3883,7 @@ define @vp_ctlz_zero_undef_nxv1i8( %va, @llvm.vp.ctlz.nxv1i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3913,7 +3913,7 @@ define @vp_ctlz_zero_undef_nxv1i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3942,7 +3942,7 @@ define @vp_ctlz_zero_undef_nxv2i8( %va, @llvm.vp.ctlz.nxv2i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3972,7 +3972,7 @@ define @vp_ctlz_zero_undef_nxv2i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4001,7 +4001,7 @@ define @vp_ctlz_zero_undef_nxv4i8( %va, @llvm.vp.ctlz.nxv4i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4031,7 +4031,7 @@ define @vp_ctlz_zero_undef_nxv4i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4060,7 +4060,7 @@ define @vp_ctlz_zero_undef_nxv8i8( %va, @llvm.vp.ctlz.nxv8i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4090,7 +4090,7 @@ define @vp_ctlz_zero_undef_nxv8i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4119,7 +4119,7 @@ define @vp_ctlz_zero_undef_nxv16i8( %va, @llvm.vp.ctlz.nxv16i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4149,7 +4149,7 @@ define @vp_ctlz_zero_undef_nxv16i8_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4178,7 +4178,7 @@ define @vp_ctlz_zero_undef_nxv32i8( %va, @llvm.vp.ctlz.nxv32i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4208,7 +4208,7 @@ define @vp_ctlz_zero_undef_nxv32i8_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv32i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4237,7 +4237,7 @@ define @vp_ctlz_zero_undef_nxv64i8( %va, @llvm.vp.ctlz.nxv64i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4267,7 +4267,7 @@ define @vp_ctlz_zero_undef_nxv64i8_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv64i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv64i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -4338,7 +4338,7 @@ define @vp_ctlz_zero_undef_nxv1i16( %va, @llvm.vp.ctlz.nxv1i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4410,7 +4410,7 @@ define @vp_ctlz_zero_undef_nxv1i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4481,7 +4481,7 @@ define @vp_ctlz_zero_undef_nxv2i16( %va, @llvm.vp.ctlz.nxv2i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4553,7 +4553,7 @@ define @vp_ctlz_zero_undef_nxv2i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4624,7 +4624,7 @@ define @vp_ctlz_zero_undef_nxv4i16( %va, @llvm.vp.ctlz.nxv4i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4696,7 +4696,7 @@ define @vp_ctlz_zero_undef_nxv4i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4767,7 +4767,7 @@ define @vp_ctlz_zero_undef_nxv8i16( %va, @llvm.vp.ctlz.nxv8i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4839,7 +4839,7 @@ define @vp_ctlz_zero_undef_nxv8i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4910,7 +4910,7 @@ define @vp_ctlz_zero_undef_nxv16i16( %va, ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call @llvm.vp.ctlz.nxv16i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4982,7 +4982,7 @@ define @vp_ctlz_zero_undef_nxv16i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -5053,7 +5053,7 @@ define @vp_ctlz_zero_undef_nxv32i16( %va, ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call @llvm.vp.ctlz.nxv32i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -5125,7 +5125,7 @@ define @vp_ctlz_zero_undef_nxv32i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv32i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv32i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -5202,7 +5202,7 @@ define @vp_ctlz_zero_undef_nxv1i32( %va, @llvm.vp.ctlz.nxv1i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5280,7 +5280,7 @@ define @vp_ctlz_zero_undef_nxv1i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5357,7 +5357,7 @@ define @vp_ctlz_zero_undef_nxv2i32( %va, @llvm.vp.ctlz.nxv2i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5435,7 +5435,7 @@ define @vp_ctlz_zero_undef_nxv2i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5512,7 +5512,7 @@ define @vp_ctlz_zero_undef_nxv4i32( %va, @llvm.vp.ctlz.nxv4i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5590,7 +5590,7 @@ define @vp_ctlz_zero_undef_nxv4i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5667,7 +5667,7 @@ define @vp_ctlz_zero_undef_nxv8i32( %va, @llvm.vp.ctlz.nxv8i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5745,7 +5745,7 @@ define @vp_ctlz_zero_undef_nxv8i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5822,7 +5822,7 @@ define @vp_ctlz_zero_undef_nxv16i32( %va, ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call @llvm.vp.ctlz.nxv16i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5900,7 +5900,7 @@ define @vp_ctlz_zero_undef_nxv16i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -6009,7 +6009,7 @@ define @vp_ctlz_zero_undef_nxv1i64( %va, @llvm.vp.ctlz.nxv1i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6119,7 +6119,7 @@ define @vp_ctlz_zero_undef_nxv1i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv1i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv1i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6228,7 +6228,7 @@ define @vp_ctlz_zero_undef_nxv2i64( %va, @llvm.vp.ctlz.nxv2i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6338,7 +6338,7 @@ define @vp_ctlz_zero_undef_nxv2i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv2i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv2i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6447,7 +6447,7 @@ define @vp_ctlz_zero_undef_nxv4i64( %va, @llvm.vp.ctlz.nxv4i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6557,7 +6557,7 @@ define @vp_ctlz_zero_undef_nxv4i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv4i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv4i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6666,7 +6666,7 @@ define @vp_ctlz_zero_undef_nxv7i64( %va, @llvm.vp.ctlz.nxv7i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6776,7 +6776,7 @@ define @vp_ctlz_zero_undef_nxv7i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv7i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv7i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6885,7 +6885,7 @@ define @vp_ctlz_zero_undef_nxv8i64( %va, @llvm.vp.ctlz.nxv8i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6995,7 +6995,7 @@ define @vp_ctlz_zero_undef_nxv8i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv8i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv8i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -7322,7 +7322,7 @@ define @vp_ctlz_zero_undef_nxv16i64( %va, ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret - %v = call @llvm.vp.ctlz.nxv16i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -7545,6 +7545,6 @@ define @vp_ctlz_zero_undef_nxv16i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.ctlz.nxv16i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.ctlz.nxv16i64( %va, i1 true, %m, i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll index 2a5bb98..e76a4d2 100644 --- a/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -declare @llvm.vp.cttz.nxv1i8(, , i32, i1 immarg) +declare @llvm.vp.cttz.nxv1i8(, i1 immarg, , i32) define @vp_cttz_nxv1i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_nxv1i8: @@ -27,7 +27,7 @@ define @vp_cttz_nxv1i8( %va, @llvm.vp.cttz.nxv1i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -56,11 +56,11 @@ define @vp_cttz_nxv1i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv2i8(, , i32, i1) +declare @llvm.vp.cttz.nxv2i8(, i1 immarg, , i32) define @vp_cttz_nxv2i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_nxv2i8: @@ -83,7 +83,7 @@ define @vp_cttz_nxv2i8( %va, @llvm.vp.cttz.nxv2i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -112,11 +112,11 @@ define @vp_cttz_nxv2i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv4i8(, , i32, i1) +declare @llvm.vp.cttz.nxv4i8(, i1 immarg, , i32) define @vp_cttz_nxv4i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_nxv4i8: @@ -139,7 +139,7 @@ define @vp_cttz_nxv4i8( %va, @llvm.vp.cttz.nxv4i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -168,11 +168,11 @@ define @vp_cttz_nxv4i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv8i8(, , i32, i1) +declare @llvm.vp.cttz.nxv8i8(, i1 immarg, , i32) define @vp_cttz_nxv8i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_nxv8i8: @@ -195,7 +195,7 @@ define @vp_cttz_nxv8i8( %va, @llvm.vp.cttz.nxv8i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -224,11 +224,11 @@ define @vp_cttz_nxv8i8_unmasked( %va, i32 zer ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv16i8(, , i32, i1) +declare @llvm.vp.cttz.nxv16i8(, i1 immarg, , i32) define @vp_cttz_nxv16i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_nxv16i8: @@ -251,7 +251,7 @@ define @vp_cttz_nxv16i8( %va, @llvm.vp.cttz.nxv16i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -280,11 +280,11 @@ define @vp_cttz_nxv16i8_unmasked( %va, i32 ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv32i8(, , i32, i1) +declare @llvm.vp.cttz.nxv32i8(, i1 immarg, , i32) define @vp_cttz_nxv32i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_nxv32i8: @@ -307,7 +307,7 @@ define @vp_cttz_nxv32i8( %va, @llvm.vp.cttz.nxv32i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv32i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -336,11 +336,11 @@ define @vp_cttz_nxv32i8_unmasked( %va, i32 ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv32i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv64i8(, , i32, i1) +declare @llvm.vp.cttz.nxv64i8(, i1 immarg, , i32) define @vp_cttz_nxv64i8( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_nxv64i8: @@ -363,7 +363,7 @@ define @vp_cttz_nxv64i8( %va, @llvm.vp.cttz.nxv64i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv64i8( %va, i1 false, %m, i32 %evl) ret %v } @@ -392,11 +392,11 @@ define @vp_cttz_nxv64i8_unmasked( %va, i32 ; CHECK-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv64i8( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv64i8( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv1i16(, , i32, i1) +declare @llvm.vp.cttz.nxv1i16(, i1 immarg, , i32) define @vp_cttz_nxv1i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv1i16: @@ -454,7 +454,7 @@ define @vp_cttz_nxv1i16( %va, @llvm.vp.cttz.nxv1i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -520,11 +520,11 @@ define @vp_cttz_nxv1i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv2i16(, , i32, i1) +declare @llvm.vp.cttz.nxv2i16(, i1 immarg, , i32) define @vp_cttz_nxv2i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv2i16: @@ -582,7 +582,7 @@ define @vp_cttz_nxv2i16( %va, @llvm.vp.cttz.nxv2i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -648,11 +648,11 @@ define @vp_cttz_nxv2i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv4i16(, , i32, i1) +declare @llvm.vp.cttz.nxv4i16(, i1 immarg, , i32) define @vp_cttz_nxv4i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv4i16: @@ -710,7 +710,7 @@ define @vp_cttz_nxv4i16( %va, @llvm.vp.cttz.nxv4i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -776,11 +776,11 @@ define @vp_cttz_nxv4i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv8i16(, , i32, i1) +declare @llvm.vp.cttz.nxv8i16(, i1 immarg, , i32) define @vp_cttz_nxv8i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv8i16: @@ -838,7 +838,7 @@ define @vp_cttz_nxv8i16( %va, @llvm.vp.cttz.nxv8i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -904,11 +904,11 @@ define @vp_cttz_nxv8i16_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv16i16(, , i32, i1) +declare @llvm.vp.cttz.nxv16i16(, i1 immarg, , i32) define @vp_cttz_nxv16i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv16i16: @@ -966,7 +966,7 @@ define @vp_cttz_nxv16i16( %va, @llvm.vp.cttz.nxv16i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -1032,11 +1032,11 @@ define @vp_cttz_nxv16i16_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv32i16(, , i32, i1) +declare @llvm.vp.cttz.nxv32i16(, i1 immarg, , i32) define @vp_cttz_nxv32i16( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv32i16: @@ -1094,7 +1094,7 @@ define @vp_cttz_nxv32i16( %va, @llvm.vp.cttz.nxv32i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv32i16( %va, i1 false, %m, i32 %evl) ret %v } @@ -1160,11 +1160,11 @@ define @vp_cttz_nxv32i16_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i16( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv32i16( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv1i32(, , i32, i1) +declare @llvm.vp.cttz.nxv1i32(, i1 immarg, , i32) define @vp_cttz_nxv1i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv1i32: @@ -1224,7 +1224,7 @@ define @vp_cttz_nxv1i32( %va, @llvm.vp.cttz.nxv1i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1292,11 +1292,11 @@ define @vp_cttz_nxv1i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv2i32(, , i32, i1) +declare @llvm.vp.cttz.nxv2i32(, i1 immarg, , i32) define @vp_cttz_nxv2i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv2i32: @@ -1356,7 +1356,7 @@ define @vp_cttz_nxv2i32( %va, @llvm.vp.cttz.nxv2i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1424,11 +1424,11 @@ define @vp_cttz_nxv2i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv4i32(, , i32, i1) +declare @llvm.vp.cttz.nxv4i32(, i1 immarg, , i32) define @vp_cttz_nxv4i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv4i32: @@ -1488,7 +1488,7 @@ define @vp_cttz_nxv4i32( %va, @llvm.vp.cttz.nxv4i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1556,11 +1556,11 @@ define @vp_cttz_nxv4i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv8i32(, , i32, i1) +declare @llvm.vp.cttz.nxv8i32(, i1 immarg, , i32) define @vp_cttz_nxv8i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv8i32: @@ -1620,7 +1620,7 @@ define @vp_cttz_nxv8i32( %va, @llvm.vp.cttz.nxv8i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1688,11 +1688,11 @@ define @vp_cttz_nxv8i32_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv16i32(, , i32, i1) +declare @llvm.vp.cttz.nxv16i32(, i1 immarg, , i32) define @vp_cttz_nxv16i32( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv16i32: @@ -1752,7 +1752,7 @@ define @vp_cttz_nxv16i32( %va, @llvm.vp.cttz.nxv16i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i32( %va, i1 false, %m, i32 %evl) ret %v } @@ -1820,11 +1820,11 @@ define @vp_cttz_nxv16i32_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i32( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i32( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv1i64(, , i32, i1) +declare @llvm.vp.cttz.nxv1i64(, i1 immarg, , i32) define @vp_cttz_nxv1i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv1i64: @@ -1910,7 +1910,7 @@ define @vp_cttz_nxv1i64( %va, @llvm.vp.cttz.nxv1i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2004,11 +2004,11 @@ define @vp_cttz_nxv1i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv1i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv2i64(, , i32, i1) +declare @llvm.vp.cttz.nxv2i64(, i1 immarg, , i32) define @vp_cttz_nxv2i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv2i64: @@ -2094,7 +2094,7 @@ define @vp_cttz_nxv2i64( %va, @llvm.vp.cttz.nxv2i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2188,11 +2188,11 @@ define @vp_cttz_nxv2i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv2i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv4i64(, , i32, i1) +declare @llvm.vp.cttz.nxv4i64(, i1 immarg, , i32) define @vp_cttz_nxv4i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv4i64: @@ -2278,7 +2278,7 @@ define @vp_cttz_nxv4i64( %va, @llvm.vp.cttz.nxv4i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2372,11 +2372,11 @@ define @vp_cttz_nxv4i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv4i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv7i64(, , i32, i1) +declare @llvm.vp.cttz.nxv7i64(, i1 immarg, , i32) define @vp_cttz_nxv7i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv7i64: @@ -2462,7 +2462,7 @@ define @vp_cttz_nxv7i64( %va, @llvm.vp.cttz.nxv7i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv7i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2556,11 +2556,11 @@ define @vp_cttz_nxv7i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv7i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv7i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv8i64(, , i32, i1) +declare @llvm.vp.cttz.nxv8i64(, i1 immarg, , i32) define @vp_cttz_nxv8i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv8i64: @@ -2646,7 +2646,7 @@ define @vp_cttz_nxv8i64( %va, @llvm.vp.cttz.nxv8i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -2740,11 +2740,11 @@ define @vp_cttz_nxv8i64_unmasked( %va, i32 ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv8i64( %va, i1 false, %m, i32 %evl) ret %v } -declare @llvm.vp.cttz.nxv16i64(, , i32, i1) +declare @llvm.vp.cttz.nxv16i64(, i1 immarg, , i32) define @vp_cttz_nxv16i64( %va, %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_nxv16i64: @@ -3029,7 +3029,7 @@ define @vp_cttz_nxv16i64( %va, @llvm.vp.cttz.nxv16i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -3273,7 +3273,7 @@ define @vp_cttz_nxv16i64_unmasked( %va, i ; RV64-NEXT: ret %head = insertelement poison, i1 false, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i64( %va, %m, i32 %evl, i1 false) + %v = call @llvm.vp.cttz.nxv16i64( %va, i1 false, %m, i32 %evl) ret %v } @@ -3298,7 +3298,7 @@ define @vp_cttz_zero_undef_nxv1i8( %va, @llvm.vp.cttz.nxv1i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3325,7 +3325,7 @@ define @vp_cttz_zero_undef_nxv1i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3351,7 +3351,7 @@ define @vp_cttz_zero_undef_nxv2i8( %va, @llvm.vp.cttz.nxv2i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3378,7 +3378,7 @@ define @vp_cttz_zero_undef_nxv2i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3404,7 +3404,7 @@ define @vp_cttz_zero_undef_nxv4i8( %va, @llvm.vp.cttz.nxv4i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3431,7 +3431,7 @@ define @vp_cttz_zero_undef_nxv4i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3457,7 +3457,7 @@ define @vp_cttz_zero_undef_nxv8i8( %va, @llvm.vp.cttz.nxv8i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3484,7 +3484,7 @@ define @vp_cttz_zero_undef_nxv8i8_unmasked( % ; CHECK-NEXT: ret %head = insertelement poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3510,7 +3510,7 @@ define @vp_cttz_zero_undef_nxv16i8( %va, @llvm.vp.cttz.nxv16i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3537,7 +3537,7 @@ define @vp_cttz_zero_undef_nxv16i8_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3563,7 +3563,7 @@ define @vp_cttz_zero_undef_nxv32i8( %va, @llvm.vp.cttz.nxv32i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv32i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3590,7 +3590,7 @@ define @vp_cttz_zero_undef_nxv32i8_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv32i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3616,7 +3616,7 @@ define @vp_cttz_zero_undef_nxv64i8( %va, @llvm.vp.cttz.nxv64i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv64i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3643,7 +3643,7 @@ define @vp_cttz_zero_undef_nxv64i8_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv64i8( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv64i8( %va, i1 true, %m, i32 %evl) ret %v } @@ -3704,7 +3704,7 @@ define @vp_cttz_zero_undef_nxv1i16( %va, @llvm.vp.cttz.nxv1i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -3766,7 +3766,7 @@ define @vp_cttz_zero_undef_nxv1i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -3827,7 +3827,7 @@ define @vp_cttz_zero_undef_nxv2i16( %va, @llvm.vp.cttz.nxv2i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -3889,7 +3889,7 @@ define @vp_cttz_zero_undef_nxv2i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -3950,7 +3950,7 @@ define @vp_cttz_zero_undef_nxv4i16( %va, @llvm.vp.cttz.nxv4i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4012,7 +4012,7 @@ define @vp_cttz_zero_undef_nxv4i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4073,7 +4073,7 @@ define @vp_cttz_zero_undef_nxv8i16( %va, @llvm.vp.cttz.nxv8i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4135,7 +4135,7 @@ define @vp_cttz_zero_undef_nxv8i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4196,7 +4196,7 @@ define @vp_cttz_zero_undef_nxv16i16( %va, ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call @llvm.vp.cttz.nxv16i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4258,7 +4258,7 @@ define @vp_cttz_zero_undef_nxv16i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4319,7 +4319,7 @@ define @vp_cttz_zero_undef_nxv32i16( %va, ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call @llvm.vp.cttz.nxv32i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv32i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4381,7 +4381,7 @@ define @vp_cttz_zero_undef_nxv32i16_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv32i16( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv32i16( %va, i1 true, %m, i32 %evl) ret %v } @@ -4444,7 +4444,7 @@ define @vp_cttz_zero_undef_nxv1i32( %va, @llvm.vp.cttz.nxv1i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4508,7 +4508,7 @@ define @vp_cttz_zero_undef_nxv1i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4571,7 +4571,7 @@ define @vp_cttz_zero_undef_nxv2i32( %va, @llvm.vp.cttz.nxv2i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4635,7 +4635,7 @@ define @vp_cttz_zero_undef_nxv2i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4698,7 +4698,7 @@ define @vp_cttz_zero_undef_nxv4i32( %va, @llvm.vp.cttz.nxv4i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4762,7 +4762,7 @@ define @vp_cttz_zero_undef_nxv4i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4825,7 +4825,7 @@ define @vp_cttz_zero_undef_nxv8i32( %va, @llvm.vp.cttz.nxv8i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4889,7 +4889,7 @@ define @vp_cttz_zero_undef_nxv8i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -4952,7 +4952,7 @@ define @vp_cttz_zero_undef_nxv16i32( %va, ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call @llvm.vp.cttz.nxv16i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5016,7 +5016,7 @@ define @vp_cttz_zero_undef_nxv16i32_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i32( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i32( %va, i1 true, %m, i32 %evl) ret %v } @@ -5105,7 +5105,7 @@ define @vp_cttz_zero_undef_nxv1i64( %va, @llvm.vp.cttz.nxv1i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5195,7 +5195,7 @@ define @vp_cttz_zero_undef_nxv1i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv1i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv1i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5284,7 +5284,7 @@ define @vp_cttz_zero_undef_nxv2i64( %va, @llvm.vp.cttz.nxv2i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5374,7 +5374,7 @@ define @vp_cttz_zero_undef_nxv2i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv2i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv2i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5463,7 +5463,7 @@ define @vp_cttz_zero_undef_nxv4i64( %va, @llvm.vp.cttz.nxv4i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5553,7 +5553,7 @@ define @vp_cttz_zero_undef_nxv4i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv4i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv4i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5642,7 +5642,7 @@ define @vp_cttz_zero_undef_nxv7i64( %va, @llvm.vp.cttz.nxv7i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv7i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5732,7 +5732,7 @@ define @vp_cttz_zero_undef_nxv7i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv7i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv7i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5821,7 +5821,7 @@ define @vp_cttz_zero_undef_nxv8i64( %va, @llvm.vp.cttz.nxv8i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -5911,7 +5911,7 @@ define @vp_cttz_zero_undef_nxv8i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv8i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv8i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6198,7 +6198,7 @@ define @vp_cttz_zero_undef_nxv16i64( %va, ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret - %v = call @llvm.vp.cttz.nxv16i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i64( %va, i1 true, %m, i32 %evl) ret %v } @@ -6381,6 +6381,6 @@ define @vp_cttz_zero_undef_nxv16i64_unmasked( poison, i1 true, i32 0 %m = shufflevector %head, poison, zeroinitializer - %v = call @llvm.vp.cttz.nxv16i64( %va, %m, i32 %evl, i1 true) + %v = call @llvm.vp.cttz.nxv16i64( %va, i1 true, %m, i32 %evl) ret %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll index fd22f6e..497c580 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs-vp.ll @@ -1,10 +1,9 @@ -; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=ilp32d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK -declare <2 x i8> @llvm.vp.abs.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) +declare <2 x i8> @llvm.vp.abs.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32) define <2 x i8> @vp_abs_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v2i8: @@ -13,7 +12,7 @@ define <2 x i8> @vp_abs_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -28,11 +27,11 @@ define <2 x i8> @vp_abs_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i8> @llvm.vp.abs.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } -declare <4 x i8> @llvm.vp.abs.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) +declare <4 x i8> @llvm.vp.abs.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32) define <4 x i8> @vp_abs_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v4i8: @@ -41,7 +40,7 @@ define <4 x i8> @vp_abs_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -56,11 +55,11 @@ define <4 x i8> @vp_abs_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i8> @llvm.vp.abs.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } -declare <8 x i8> @llvm.vp.abs.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) +declare <8 x i8> @llvm.vp.abs.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32) define <8 x i8> @vp_abs_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v8i8: @@ -69,7 +68,7 @@ define <8 x i8> @vp_abs_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -84,11 +83,11 @@ define <8 x i8> @vp_abs_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i8> @llvm.vp.abs.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } -declare <16 x i8> @llvm.vp.abs.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) +declare <16 x i8> @llvm.vp.abs.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32) define <16 x i8> @vp_abs_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v16i8: @@ -97,7 +96,7 @@ define <16 x i8> @vp_abs_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -112,11 +111,11 @@ define <16 x i8> @vp_abs_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i8> @llvm.vp.abs.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } -declare <2 x i16> @llvm.vp.abs.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) +declare <2 x i16> @llvm.vp.abs.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32) define <2 x i16> @vp_abs_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v2i16: @@ -125,7 +124,7 @@ define <2 x i16> @vp_abs_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -140,11 +139,11 @@ define <2 x i16> @vp_abs_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i16> @llvm.vp.abs.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } -declare <4 x i16> @llvm.vp.abs.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) +declare <4 x i16> @llvm.vp.abs.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32) define <4 x i16> @vp_abs_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v4i16: @@ -153,7 +152,7 @@ define <4 x i16> @vp_abs_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -168,11 +167,11 @@ define <4 x i16> @vp_abs_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i16> @llvm.vp.abs.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } -declare <8 x i16> @llvm.vp.abs.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) +declare <8 x i16> @llvm.vp.abs.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32) define <8 x i16> @vp_abs_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v8i16: @@ -181,7 +180,7 @@ define <8 x i16> @vp_abs_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -196,11 +195,11 @@ define <8 x i16> @vp_abs_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i16> @llvm.vp.abs.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } -declare <16 x i16> @llvm.vp.abs.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) +declare <16 x i16> @llvm.vp.abs.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32) define <16 x i16> @vp_abs_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v16i16: @@ -209,7 +208,7 @@ define <16 x i16> @vp_abs_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret - %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -224,11 +223,11 @@ define <16 x i16> @vp_abs_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i16> @llvm.vp.abs.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } -declare <2 x i32> @llvm.vp.abs.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) +declare <2 x i32> @llvm.vp.abs.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32) define <2 x i32> @vp_abs_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v2i32: @@ -237,7 +236,7 @@ define <2 x i32> @vp_abs_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -252,11 +251,11 @@ define <2 x i32> @vp_abs_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i32> @llvm.vp.abs.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } -declare <4 x i32> @llvm.vp.abs.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) +declare <4 x i32> @llvm.vp.abs.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32) define <4 x i32> @vp_abs_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v4i32: @@ -265,7 +264,7 @@ define <4 x i32> @vp_abs_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -280,11 +279,11 @@ define <4 x i32> @vp_abs_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i32> @llvm.vp.abs.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } -declare <8 x i32> @llvm.vp.abs.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) +declare <8 x i32> @llvm.vp.abs.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32) define <8 x i32> @vp_abs_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v8i32: @@ -293,7 +292,7 @@ define <8 x i32> @vp_abs_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret - %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -308,11 +307,11 @@ define <8 x i32> @vp_abs_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i32> @llvm.vp.abs.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } -declare <16 x i32> @llvm.vp.abs.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) +declare <16 x i32> @llvm.vp.abs.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32) define <16 x i32> @vp_abs_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v16i32: @@ -321,7 +320,7 @@ define <16 x i32> @vp_abs_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret - %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -336,11 +335,11 @@ define <16 x i32> @vp_abs_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i32> @llvm.vp.abs.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } -declare <2 x i64> @llvm.vp.abs.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) +declare <2 x i64> @llvm.vp.abs.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32) define <2 x i64> @vp_abs_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v2i64: @@ -349,7 +348,7 @@ define <2 x i64> @vp_abs_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v9, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret - %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -364,11 +363,11 @@ define <2 x i64> @vp_abs_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i64> @llvm.vp.abs.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } -declare <4 x i64> @llvm.vp.abs.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) +declare <4 x i64> @llvm.vp.abs.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32) define <4 x i64> @vp_abs_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v4i64: @@ -377,7 +376,7 @@ define <4 x i64> @vp_abs_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v10, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret - %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -392,11 +391,11 @@ define <4 x i64> @vp_abs_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i64> @llvm.vp.abs.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } -declare <8 x i64> @llvm.vp.abs.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) +declare <8 x i64> @llvm.vp.abs.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32) define <8 x i64> @vp_abs_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v8i64: @@ -405,7 +404,7 @@ define <8 x i64> @vp_abs_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vrsub.vi v12, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret - %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -420,11 +419,11 @@ define <8 x i64> @vp_abs_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i64> @llvm.vp.abs.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } -declare <15 x i64> @llvm.vp.abs.v15i64(<15 x i64>, <15 x i1>, i32, i1 immarg) +declare <15 x i64> @llvm.vp.abs.v15i64(<15 x i64>, i1 immarg, <15 x i1>, i32) define <15 x i64> @vp_abs_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v15i64: @@ -433,7 +432,7 @@ define <15 x i64> @vp_abs_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret - %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) + %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -448,11 +447,11 @@ define <15 x i64> @vp_abs_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <15 x i1> poison, i1 true, i32 0 %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) + %v = call <15 x i64> @llvm.vp.abs.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } -declare <16 x i64> @llvm.vp.abs.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) +declare <16 x i64> @llvm.vp.abs.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32) define <16 x i64> @vp_abs_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v16i64: @@ -461,7 +460,7 @@ define <16 x i64> @vp_abs_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v16, v8, 0, v0.t ; CHECK-NEXT: vmax.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret - %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -476,11 +475,11 @@ define <16 x i64> @vp_abs_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i64> @llvm.vp.abs.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } -declare <32 x i64> @llvm.vp.abs.v32i64(<32 x i64>, <32 x i1>, i32, i1 immarg) +declare <32 x i64> @llvm.vp.abs.v32i64(<32 x i64>, i1 immarg, <32 x i1>, i32) define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_abs_v32i64: @@ -505,7 +504,7 @@ define <32 x i64> @vp_abs_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) ; CHECK-NEXT: vrsub.vi v24, v16, 0, v0.t ; CHECK-NEXT: vmax.vv v16, v16, v24, v0.t ; CHECK-NEXT: ret - %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) + %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -533,6 +532,6 @@ define <32 x i64> @vp_abs_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <32 x i1> poison, i1 true, i32 0 %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) + %v = call <32 x i64> @llvm.vp.abs.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll index 969109b..e2e9fd8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz-vp.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) +declare <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32) define <2 x i8> @vp_ctlz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_v2i8: @@ -30,7 +30,7 @@ define <2 x i8> @vp_ctlz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -62,11 +62,11 @@ define <2 x i8> @vp_ctlz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } -declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) +declare <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32) define <4 x i8> @vp_ctlz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_v4i8: @@ -92,7 +92,7 @@ define <4 x i8> @vp_ctlz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -124,11 +124,11 @@ define <4 x i8> @vp_ctlz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } -declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) +declare <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32) define <8 x i8> @vp_ctlz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_v8i8: @@ -154,7 +154,7 @@ define <8 x i8> @vp_ctlz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -186,11 +186,11 @@ define <8 x i8> @vp_ctlz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } -declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) +declare <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32) define <16 x i8> @vp_ctlz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_v16i8: @@ -216,7 +216,7 @@ define <16 x i8> @vp_ctlz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -248,11 +248,11 @@ define <16 x i8> @vp_ctlz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } -declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) +declare <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32) define <2 x i16> @vp_ctlz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v2i16: @@ -320,7 +320,7 @@ define <2 x i16> @vp_ctlz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -396,11 +396,11 @@ define <2 x i16> @vp_ctlz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } -declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) +declare <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32) define <4 x i16> @vp_ctlz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v4i16: @@ -468,7 +468,7 @@ define <4 x i16> @vp_ctlz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -544,11 +544,11 @@ define <4 x i16> @vp_ctlz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } -declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) +declare <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32) define <8 x i16> @vp_ctlz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v8i16: @@ -616,7 +616,7 @@ define <8 x i16> @vp_ctlz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -692,11 +692,11 @@ define <8 x i16> @vp_ctlz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } -declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) +declare <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32) define <16 x i16> @vp_ctlz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v16i16: @@ -764,7 +764,7 @@ define <16 x i16> @vp_ctlz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -840,11 +840,11 @@ define <16 x i16> @vp_ctlz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } -declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) +declare <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32) define <2 x i32> @vp_ctlz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v2i32: @@ -918,7 +918,7 @@ define <2 x i32> @vp_ctlz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -1000,11 +1000,11 @@ define <2 x i32> @vp_ctlz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } -declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) +declare <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32) define <4 x i32> @vp_ctlz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v4i32: @@ -1078,7 +1078,7 @@ define <4 x i32> @vp_ctlz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -1160,11 +1160,11 @@ define <4 x i32> @vp_ctlz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } -declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) +declare <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32) define <8 x i32> @vp_ctlz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v8i32: @@ -1238,7 +1238,7 @@ define <8 x i32> @vp_ctlz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1320,11 +1320,11 @@ define <8 x i32> @vp_ctlz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } -declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) +declare <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32) define <16 x i32> @vp_ctlz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v16i32: @@ -1398,7 +1398,7 @@ define <16 x i32> @vp_ctlz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1480,11 +1480,11 @@ define <16 x i32> @vp_ctlz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } -declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) +declare <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32) define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v2i64: @@ -1581,7 +1581,7 @@ define <2 x i64> @vp_ctlz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1686,11 +1686,11 @@ define <2 x i64> @vp_ctlz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } -declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) +declare <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32) define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v4i64: @@ -1787,7 +1787,7 @@ define <4 x i64> @vp_ctlz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1892,11 +1892,11 @@ define <4 x i64> @vp_ctlz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } -declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) +declare <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32) define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v8i64: @@ -1993,7 +1993,7 @@ define <8 x i64> @vp_ctlz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -2098,11 +2098,11 @@ define <8 x i64> @vp_ctlz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } -declare <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64>, <15 x i1>, i32, i1 immarg) +declare <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64>, i1 immarg, <15 x i1>, i32) define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v15i64: @@ -2199,7 +2199,7 @@ define <15 x i64> @vp_ctlz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) + %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -2304,11 +2304,11 @@ define <15 x i64> @vp_ctlz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <15 x i1> poison, i1 false, i32 0 %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) + %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } -declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) +declare <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32) define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v16i64: @@ -2405,7 +2405,7 @@ define <16 x i64> @vp_ctlz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -2510,11 +2510,11 @@ define <16 x i64> @vp_ctlz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } -declare <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64>, <32 x i1>, i32, i1 immarg) +declare <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64>, i1 immarg, <32 x i1>, i32) define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_ctlz_v32i64: @@ -2885,7 +2885,7 @@ define <32 x i64> @vp_ctlz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret - %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) + %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -3144,7 +3144,7 @@ define <32 x i64> @vp_ctlz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <32 x i1> poison, i1 false, i32 0 %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) + %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -3172,7 +3172,7 @@ define <2 x i8> @vp_ctlz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -3202,7 +3202,7 @@ define <2 x i8> @vp_ctlz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i8> @llvm.vp.ctlz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -3230,7 +3230,7 @@ define <4 x i8> @vp_ctlz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -3260,7 +3260,7 @@ define <4 x i8> @vp_ctlz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i8> @llvm.vp.ctlz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -3288,7 +3288,7 @@ define <8 x i8> @vp_ctlz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -3318,7 +3318,7 @@ define <8 x i8> @vp_ctlz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i8> @llvm.vp.ctlz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -3346,7 +3346,7 @@ define <16 x i8> @vp_ctlz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zero ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -3376,7 +3376,7 @@ define <16 x i8> @vp_ctlz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext % ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i8> @llvm.vp.ctlz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -3446,7 +3446,7 @@ define <2 x i16> @vp_ctlz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -3518,7 +3518,7 @@ define <2 x i16> @vp_ctlz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i16> @llvm.vp.ctlz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -3588,7 +3588,7 @@ define <4 x i16> @vp_ctlz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -3660,7 +3660,7 @@ define <4 x i16> @vp_ctlz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i16> @llvm.vp.ctlz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -3730,7 +3730,7 @@ define <8 x i16> @vp_ctlz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -3802,7 +3802,7 @@ define <8 x i16> @vp_ctlz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i16> @llvm.vp.ctlz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -3872,7 +3872,7 @@ define <16 x i16> @vp_ctlz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 z ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -3944,7 +3944,7 @@ define <16 x i16> @vp_ctlz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i16> @llvm.vp.ctlz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -4020,7 +4020,7 @@ define <2 x i32> @vp_ctlz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -4098,7 +4098,7 @@ define <2 x i32> @vp_ctlz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i32> @llvm.vp.ctlz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -4174,7 +4174,7 @@ define <4 x i32> @vp_ctlz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -4252,7 +4252,7 @@ define <4 x i32> @vp_ctlz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i32> @llvm.vp.ctlz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -4328,7 +4328,7 @@ define <8 x i32> @vp_ctlz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -4406,7 +4406,7 @@ define <8 x i32> @vp_ctlz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i32> @llvm.vp.ctlz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -4482,7 +4482,7 @@ define <16 x i32> @vp_ctlz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 z ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -4560,7 +4560,7 @@ define <16 x i32> @vp_ctlz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i32> @llvm.vp.ctlz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -4659,7 +4659,7 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -4760,7 +4760,7 @@ define <2 x i64> @vp_ctlz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i64> @llvm.vp.ctlz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -4859,7 +4859,7 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -4960,7 +4960,7 @@ define <4 x i64> @vp_ctlz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i64> @llvm.vp.ctlz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -5059,7 +5059,7 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -5160,7 +5160,7 @@ define <8 x i64> @vp_ctlz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i64> @llvm.vp.ctlz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -5259,7 +5259,7 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) + %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -5360,7 +5360,7 @@ define <15 x i64> @vp_ctlz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <15 x i1> poison, i1 true, i32 0 %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) + %v = call <15 x i64> @llvm.vp.ctlz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -5459,7 +5459,7 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -5560,7 +5560,7 @@ define <16 x i64> @vp_ctlz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i64> @llvm.vp.ctlz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -5933,7 +5933,7 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret - %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) + %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -6165,6 +6165,6 @@ define <32 x i64> @vp_ctlz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <32 x i1> poison, i1 true, i32 0 %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) + %v = call <32 x i64> @llvm.vp.ctlz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll index f390e9b..02e8b0c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz-vp.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v,+m -target-abi=lp64d -riscv-v-vector-bits-min=128 \ ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64 -declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, <2 x i1>, i32, i1 immarg) +declare <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8>, i1 immarg, <2 x i1>, i32) define <2 x i8> @vp_cttz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_v2i8: @@ -27,7 +27,7 @@ define <2 x i8> @vp_cttz_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -56,11 +56,11 @@ define <2 x i8> @vp_cttz_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } -declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, <4 x i1>, i32, i1 immarg) +declare <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8>, i1 immarg, <4 x i1>, i32) define <4 x i8> @vp_cttz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_v4i8: @@ -83,7 +83,7 @@ define <4 x i8> @vp_cttz_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -112,11 +112,11 @@ define <4 x i8> @vp_cttz_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } -declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, <8 x i1>, i32, i1 immarg) +declare <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8>, i1 immarg, <8 x i1>, i32) define <8 x i8> @vp_cttz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_v8i8: @@ -139,7 +139,7 @@ define <8 x i8> @vp_cttz_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -168,11 +168,11 @@ define <8 x i8> @vp_cttz_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } -declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, <16 x i1>, i32, i1 immarg) +declare <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8>, i1 immarg, <16 x i1>, i32) define <16 x i8> @vp_cttz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_cttz_v16i8: @@ -195,7 +195,7 @@ define <16 x i8> @vp_cttz_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zeroext %evl) { ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -224,11 +224,11 @@ define <16 x i8> @vp_cttz_v16i8_unmasked(<16 x i8> %va, i32 zeroext %evl) { ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } -declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, <2 x i1>, i32, i1 immarg) +declare <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16>, i1 immarg, <2 x i1>, i32) define <2 x i16> @vp_cttz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v2i16: @@ -286,7 +286,7 @@ define <2 x i16> @vp_cttz_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -352,11 +352,11 @@ define <2 x i16> @vp_cttz_v2i16_unmasked(<2 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } -declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, <4 x i1>, i32, i1 immarg) +declare <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16>, i1 immarg, <4 x i1>, i32) define <4 x i16> @vp_cttz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v4i16: @@ -414,7 +414,7 @@ define <4 x i16> @vp_cttz_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -480,11 +480,11 @@ define <4 x i16> @vp_cttz_v4i16_unmasked(<4 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } -declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, <8 x i1>, i32, i1 immarg) +declare <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16>, i1 immarg, <8 x i1>, i32) define <8 x i16> @vp_cttz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v8i16: @@ -542,7 +542,7 @@ define <8 x i16> @vp_cttz_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -608,11 +608,11 @@ define <8 x i16> @vp_cttz_v8i16_unmasked(<8 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } -declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, <16 x i1>, i32, i1 immarg) +declare <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16>, i1 immarg, <16 x i1>, i32) define <16 x i16> @vp_cttz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v16i16: @@ -670,7 +670,7 @@ define <16 x i16> @vp_cttz_v16i16(<16 x i16> %va, <16 x i1> %m, i32 zeroext %evl ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -736,11 +736,11 @@ define <16 x i16> @vp_cttz_v16i16_unmasked(<16 x i16> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } -declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, <2 x i1>, i32, i1 immarg) +declare <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32>, i1 immarg, <2 x i1>, i32) define <2 x i32> @vp_cttz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v2i32: @@ -800,7 +800,7 @@ define <2 x i32> @vp_cttz_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -868,11 +868,11 @@ define <2 x i32> @vp_cttz_v2i32_unmasked(<2 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } -declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, <4 x i1>, i32, i1 immarg) +declare <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32>, i1 immarg, <4 x i1>, i32) define <4 x i32> @vp_cttz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v4i32: @@ -932,7 +932,7 @@ define <4 x i32> @vp_cttz_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -1000,11 +1000,11 @@ define <4 x i32> @vp_cttz_v4i32_unmasked(<4 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } -declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, <8 x i1>, i32, i1 immarg) +declare <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32>, i1 immarg, <8 x i1>, i32) define <8 x i32> @vp_cttz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v8i32: @@ -1064,7 +1064,7 @@ define <8 x i32> @vp_cttz_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -1132,11 +1132,11 @@ define <8 x i32> @vp_cttz_v8i32_unmasked(<8 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } -declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, <16 x i1>, i32, i1 immarg) +declare <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32>, i1 immarg, <16 x i1>, i32) define <16 x i32> @vp_cttz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v16i32: @@ -1196,7 +1196,7 @@ define <16 x i32> @vp_cttz_v16i32(<16 x i32> %va, <16 x i1> %m, i32 zeroext %evl ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -1264,11 +1264,11 @@ define <16 x i32> @vp_cttz_v16i32_unmasked(<16 x i32> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } -declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, <2 x i1>, i32, i1 immarg) +declare <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64>, i1 immarg, <2 x i1>, i32) define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v2i64: @@ -1345,7 +1345,7 @@ define <2 x i64> @vp_cttz_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -1430,11 +1430,11 @@ define <2 x i64> @vp_cttz_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 false, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 false) + %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 false, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } -declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, <4 x i1>, i32, i1 immarg) +declare <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64>, i1 immarg, <4 x i1>, i32) define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v4i64: @@ -1511,7 +1511,7 @@ define <4 x i64> @vp_cttz_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -1596,11 +1596,11 @@ define <4 x i64> @vp_cttz_v4i64_unmasked(<4 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 false, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 false) + %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 false, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } -declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, <8 x i1>, i32, i1 immarg) +declare <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64>, i1 immarg, <8 x i1>, i32) define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v8i64: @@ -1677,7 +1677,7 @@ define <8 x i64> @vp_cttz_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroext %evl) { ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -1762,11 +1762,11 @@ define <8 x i64> @vp_cttz_v8i64_unmasked(<8 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 false, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 false) + %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 false, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } -declare <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64>, <15 x i1>, i32, i1 immarg) +declare <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64>, i1 immarg, <15 x i1>, i32) define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v15i64: @@ -1844,7 +1844,7 @@ define <15 x i64> @vp_cttz_v15i64(<15 x i64> %va, <15 x i1> %m, i32 zeroext %evl ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) + %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -1930,11 +1930,11 @@ define <15 x i64> @vp_cttz_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <15 x i1> poison, i1 false, i32 0 %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 false) + %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 false, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } -declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, <16 x i1>, i32, i1 immarg) +declare <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64>, i1 immarg, <16 x i1>, i32) define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v16i64: @@ -2012,7 +2012,7 @@ define <16 x i64> @vp_cttz_v16i64(<16 x i64> %va, <16 x i1> %m, i32 zeroext %evl ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -2098,11 +2098,11 @@ define <16 x i64> @vp_cttz_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 false, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 false) + %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 false, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } -declare <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64>, <32 x i1>, i32, i1 immarg) +declare <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64>, i1 immarg, <32 x i1>, i32) define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl) { ; RV32-LABEL: vp_cttz_v32i64: @@ -2459,7 +2459,7 @@ define <32 x i64> @vp_cttz_v32i64(<32 x i64> %va, <32 x i1> %m, i32 zeroext %evl ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret - %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) + %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -2679,7 +2679,7 @@ define <32 x i64> @vp_cttz_v32i64_unmasked(<32 x i64> %va, i32 zeroext %evl) { ; RV64-NEXT: ret %head = insertelement <32 x i1> poison, i1 false, i32 0 %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 false) + %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 false, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -2704,7 +2704,7 @@ define <2 x i8> @vp_cttz_zero_undef_v2i8(<2 x i8> %va, <2 x i1> %m, i32 zeroext ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -2731,7 +2731,7 @@ define <2 x i8> @vp_cttz_zero_undef_v2i8_unmasked(<2 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i8> @llvm.vp.cttz.v2i8(<2 x i8> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i8> %v } @@ -2756,7 +2756,7 @@ define <4 x i8> @vp_cttz_zero_undef_v4i8(<4 x i8> %va, <4 x i1> %m, i32 zeroext ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -2783,7 +2783,7 @@ define <4 x i8> @vp_cttz_zero_undef_v4i8_unmasked(<4 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i8> @llvm.vp.cttz.v4i8(<4 x i8> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i8> %v } @@ -2808,7 +2808,7 @@ define <8 x i8> @vp_cttz_zero_undef_v8i8(<8 x i8> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -2835,7 +2835,7 @@ define <8 x i8> @vp_cttz_zero_undef_v8i8_unmasked(<8 x i8> %va, i32 zeroext %evl ; CHECK-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i8> @llvm.vp.cttz.v8i8(<8 x i8> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i8> %v } @@ -2860,7 +2860,7 @@ define <16 x i8> @vp_cttz_zero_undef_v16i8(<16 x i8> %va, <16 x i1> %m, i32 zero ; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vand.vi v8, v8, 15, v0.t ; CHECK-NEXT: ret - %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -2887,7 +2887,7 @@ define <16 x i8> @vp_cttz_zero_undef_v16i8_unmasked(<16 x i8> %va, i32 zeroext % ; CHECK-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i8> @llvm.vp.cttz.v16i8(<16 x i8> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i8> %v } @@ -2947,7 +2947,7 @@ define <2 x i16> @vp_cttz_zero_undef_v2i16(<2 x i16> %va, <2 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -3009,7 +3009,7 @@ define <2 x i16> @vp_cttz_zero_undef_v2i16_unmasked(<2 x i16> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i16> @llvm.vp.cttz.v2i16(<2 x i16> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i16> %v } @@ -3069,7 +3069,7 @@ define <4 x i16> @vp_cttz_zero_undef_v4i16(<4 x i16> %va, <4 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -3131,7 +3131,7 @@ define <4 x i16> @vp_cttz_zero_undef_v4i16_unmasked(<4 x i16> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i16> @llvm.vp.cttz.v4i16(<4 x i16> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i16> %v } @@ -3191,7 +3191,7 @@ define <8 x i16> @vp_cttz_zero_undef_v8i16(<8 x i16> %va, <8 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -3253,7 +3253,7 @@ define <8 x i16> @vp_cttz_zero_undef_v8i16_unmasked(<8 x i16> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i16> @llvm.vp.cttz.v8i16(<8 x i16> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i16> %v } @@ -3313,7 +3313,7 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16(<16 x i16> %va, <16 x i1> %m, i32 z ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 8, v0.t ; RV64-NEXT: ret - %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -3375,7 +3375,7 @@ define <16 x i16> @vp_cttz_zero_undef_v16i16_unmasked(<16 x i16> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i16> @llvm.vp.cttz.v16i16(<16 x i16> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i16> %v } @@ -3437,7 +3437,7 @@ define <2 x i32> @vp_cttz_zero_undef_v2i32(<2 x i32> %va, <2 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -3501,7 +3501,7 @@ define <2 x i32> @vp_cttz_zero_undef_v2i32_unmasked(<2 x i32> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i32> @llvm.vp.cttz.v2i32(<2 x i32> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i32> %v } @@ -3563,7 +3563,7 @@ define <4 x i32> @vp_cttz_zero_undef_v4i32(<4 x i32> %va, <4 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -3627,7 +3627,7 @@ define <4 x i32> @vp_cttz_zero_undef_v4i32_unmasked(<4 x i32> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i32> @llvm.vp.cttz.v4i32(<4 x i32> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i32> %v } @@ -3689,7 +3689,7 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32(<8 x i32> %va, <8 x i1> %m, i32 zeroe ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -3753,7 +3753,7 @@ define <8 x i32> @vp_cttz_zero_undef_v8i32_unmasked(<8 x i32> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i32> @llvm.vp.cttz.v8i32(<8 x i32> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i32> %v } @@ -3815,7 +3815,7 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32(<16 x i32> %va, <16 x i1> %m, i32 z ; RV64-NEXT: vmul.vx v8, v8, a0, v0.t ; RV64-NEXT: vsrl.vi v8, v8, 24, v0.t ; RV64-NEXT: ret - %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -3879,7 +3879,7 @@ define <16 x i32> @vp_cttz_zero_undef_v16i32_unmasked(<16 x i32> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i32> @llvm.vp.cttz.v16i32(<16 x i32> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i32> %v } @@ -3958,7 +3958,7 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64(<2 x i64> %va, <2 x i1> %m, i32 zeroe ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -4039,7 +4039,7 @@ define <2 x i64> @vp_cttz_zero_undef_v2i64_unmasked(<2 x i64> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <2 x i1> poison, i1 true, i32 0 %m = shufflevector <2 x i1> %head, <2 x i1> poison, <2 x i32> zeroinitializer - %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, <2 x i1> %m, i32 %evl, i1 true) + %v = call <2 x i64> @llvm.vp.cttz.v2i64(<2 x i64> %va, i1 true, <2 x i1> %m, i32 %evl) ret <2 x i64> %v } @@ -4118,7 +4118,7 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64(<4 x i64> %va, <4 x i1> %m, i32 zeroe ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -4199,7 +4199,7 @@ define <4 x i64> @vp_cttz_zero_undef_v4i64_unmasked(<4 x i64> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <4 x i1> poison, i1 true, i32 0 %m = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer - %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, <4 x i1> %m, i32 %evl, i1 true) + %v = call <4 x i64> @llvm.vp.cttz.v4i64(<4 x i64> %va, i1 true, <4 x i1> %m, i32 %evl) ret <4 x i64> %v } @@ -4278,7 +4278,7 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64(<8 x i64> %va, <8 x i1> %m, i32 zeroe ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -4359,7 +4359,7 @@ define <8 x i64> @vp_cttz_zero_undef_v8i64_unmasked(<8 x i64> %va, i32 zeroext % ; RV64-NEXT: ret %head = insertelement <8 x i1> poison, i1 true, i32 0 %m = shufflevector <8 x i1> %head, <8 x i1> poison, <8 x i32> zeroinitializer - %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, <8 x i1> %m, i32 %evl, i1 true) + %v = call <8 x i64> @llvm.vp.cttz.v8i64(<8 x i64> %va, i1 true, <8 x i1> %m, i32 %evl) ret <8 x i64> %v } @@ -4439,7 +4439,7 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64(<15 x i64> %va, <15 x i1> %m, i32 z ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) + %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -4521,7 +4521,7 @@ define <15 x i64> @vp_cttz_zero_undef_v15i64_unmasked(<15 x i64> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <15 x i1> poison, i1 true, i32 0 %m = shufflevector <15 x i1> %head, <15 x i1> poison, <15 x i32> zeroinitializer - %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl, i1 true) + %v = call <15 x i64> @llvm.vp.cttz.v15i64(<15 x i64> %va, i1 true, <15 x i1> %m, i32 %evl) ret <15 x i64> %v } @@ -4601,7 +4601,7 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64(<16 x i64> %va, <16 x i1> %m, i32 z ; RV64-NEXT: li a0, 56 ; RV64-NEXT: vsrl.vx v8, v8, a0, v0.t ; RV64-NEXT: ret - %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -4683,7 +4683,7 @@ define <16 x i64> @vp_cttz_zero_undef_v16i64_unmasked(<16 x i64> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <16 x i1> poison, i1 true, i32 0 %m = shufflevector <16 x i1> %head, <16 x i1> poison, <16 x i32> zeroinitializer - %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl, i1 true) + %v = call <16 x i64> @llvm.vp.cttz.v16i64(<16 x i64> %va, i1 true, <16 x i1> %m, i32 %evl) ret <16 x i64> %v } @@ -5042,7 +5042,7 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64(<32 x i64> %va, <32 x i1> %m, i32 z ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: ret - %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) + %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } @@ -5235,6 +5235,6 @@ define <32 x i64> @vp_cttz_zero_undef_v32i64_unmasked(<32 x i64> %va, i32 zeroex ; RV64-NEXT: ret %head = insertelement <32 x i1> poison, i1 true, i32 0 %m = shufflevector <32 x i1> %head, <32 x i1> poison, <32 x i32> zeroinitializer - %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, <32 x i1> %m, i32 %evl, i1 true) + %v = call <32 x i64> @llvm.vp.cttz.v32i64(<32 x i64> %va, i1 true, <32 x i1> %m, i32 %evl) ret <32 x i64> %v } diff --git a/llvm/unittests/IR/VPIntrinsicTest.cpp b/llvm/unittests/IR/VPIntrinsicTest.cpp index 668af51..e03d2e0 100644 --- a/llvm/unittests/IR/VPIntrinsicTest.cpp +++ b/llvm/unittests/IR/VPIntrinsicTest.cpp @@ -147,7 +147,7 @@ protected: << "(<8 x i16>, <8 x i16>, metadata, <8 x i1>, i32) "; Str << " declare <8 x i16> @llvm.vp.abs.v8i16" - << "(<8 x i16>, <8 x i1>, i32, i1 immarg) "; + << "(<8 x i16>, i1 immarg, <8 x i1>, i32) "; Str << " declare <8 x i16> @llvm.vp.bitreverse.v8i16" << "(<8 x i16>, <8 x i1>, i32) "; Str << " declare <8 x i16> @llvm.vp.bswap.v8i16" @@ -155,9 +155,9 @@ protected: Str << " declare <8 x i16> @llvm.vp.ctpop.v8i16" << "(<8 x i16>, <8 x i1>, i32) "; Str << " declare <8 x i16> @llvm.vp.ctlz.v8i16" - << "(<8 x i16>, <8 x i1>, i32, i1 immarg) "; + << "(<8 x i16>, i1 immarg, <8 x i1>, i32) "; Str << " declare <8 x i16> @llvm.vp.cttz.v8i16" - << "(<8 x i16>, <8 x i1>, i32, i1 immarg) "; + << "(<8 x i16>, i1 immarg, <8 x i1>, i32) "; Str << " declare <8 x i16> @llvm.vp.fshl.v8i16" << "(<8 x i16>, <8 x i16>, <8 x i16>, <8 x i1>, i32) "; Str << " declare <8 x i16> @llvm.vp.fshr.v8i16" -- 2.7.4