From 418d2b2fad7cdce5d39d0e2fdbe2460f584b5432 Mon Sep 17 00:00:00 2001 From: Yong Zhi Date: Tue, 7 Mar 2023 11:52:51 +0200 Subject: [PATCH] ASoC: SOF: Intel: mtl: Access MTL_HFPWRCTL from HDA_DSP_BAR The Host Power Management/Clock Control (ULP) Registers in the HDA BAR shadow the values of the same registers in the DSP BAR, so let's modify the latter - as done already for other accesses. Signed-off-by: Yong Zhi Reviewed-by: Ranjani Sridharan Reviewed-by: Pierre-Louis Bossart Reviewed-by: Bard Liao Signed-off-by: Peter Ujfalusi Link: https://lore.kernel.org/r/20230307095251.3058-1-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown --- sound/soc/sof/intel/mtl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/sof/intel/mtl.c b/sound/soc/sof/intel/mtl.c index 216fd07..8f0ed1c 100644 --- a/sound/soc/sof/intel/mtl.c +++ b/sound/soc/sof/intel/mtl.c @@ -256,7 +256,7 @@ static int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev) dev_err(sdev->dev, "failed to power up gated DSP domain\n"); /* make sure SoundWire is not power-gated */ - snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_HFPWRCTL, + snd_sof_dsp_update_bits(sdev, HDA_DSP_BAR, MTL_HFPWRCTL, MTL_HfPWRCTL_WPIOXPG(1), MTL_HfPWRCTL_WPIOXPG(1)); return ret; } -- 2.7.4