From 4173fffa0868688ad83aadb547b263139eb55684 Mon Sep 17 00:00:00 2001 From: Dominic Chen Date: Thu, 11 Aug 2016 04:10:56 +0000 Subject: [PATCH] [WebAssembly] Cleanup trailing whitespace Summary: Test for commit access. Subscribers: jfb, dschuff Differential Revision: https://reviews.llvm.org/D23392 llvm-svn: 278313 --- llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 5ff0085..aa40098 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -303,7 +303,7 @@ static bool IsSafeToMove(const MachineInstr *Def, const MachineInstr *Insert, // Ask LiveIntervals whether moving this virtual register use or def to // Insert will change which value numbers are seen. - // + // // If the operand is a use of a register that is also defined in the same // instruction, test that the newly defined value reaches the insert point, // since the operand will be moving along with the def. @@ -384,7 +384,7 @@ static bool OneUseDominatesOtherUses(unsigned Reg, const MachineOperand &OneUse, // // This is needed as a consequence of using implicit get_locals for // uses and implicit set_locals for defs. - if (UseInst->getDesc().getNumDefs() == 0) + if (UseInst->getDesc().getNumDefs() == 0) return false; const MachineOperand &MO = UseInst->getOperand(0); if (!MO.isReg()) -- 2.7.4