From 4125f73a287d97c7a774ad8af9b55cfea731e4e3 Mon Sep 17 00:00:00 2001 From: Zhao Yakui Date: Fri, 1 Mar 2013 10:38:13 +0800 Subject: [PATCH] Update the pixel shader for BDW rendering function Signed-off-by: Zhao Yakui --- src/i965_render.c | 8 +- src/shaders/render/Makefile.am | 28 ++++++- src/shaders/render/exa_wm_src_affine.g8a | 47 +++++++++++ src/shaders/render/exa_wm_src_affine.g8b | 4 + src/shaders/render/exa_wm_src_sample_planar.g8a | 106 ++++++++++++++++++++++++ src/shaders/render/exa_wm_src_sample_planar.g8b | 20 +++++ src/shaders/render/exa_wm_write.g8a | 83 +++++++++++++++++++ src/shaders/render/exa_wm_write.g8b | 19 +++++ src/shaders/render/exa_wm_yuv_rgb.g8a | 106 ++++++++++++++++++++++++ src/shaders/render/exa_wm_yuv_rgb.g8b | 19 +++++ 10 files changed, 435 insertions(+), 5 deletions(-) create mode 100644 src/shaders/render/exa_wm_src_affine.g8a create mode 100644 src/shaders/render/exa_wm_src_affine.g8b create mode 100644 src/shaders/render/exa_wm_src_sample_planar.g8a create mode 100644 src/shaders/render/exa_wm_src_sample_planar.g8b create mode 100644 src/shaders/render/exa_wm_write.g8a create mode 100644 src/shaders/render/exa_wm_write.g8b create mode 100644 src/shaders/render/exa_wm_yuv_rgb.g8a create mode 100644 src/shaders/render/exa_wm_yuv_rgb.g8b diff --git a/src/i965_render.c b/src/i965_render.c index 2e70697..36eca9d 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -155,10 +155,10 @@ static const uint32_t sf_kernel_static_gen8[][4] = { }; static const uint32_t ps_kernel_static_gen8[][4] = { -#include "shaders/render/exa_wm_src_affine.g7b" -#include "shaders/render/exa_wm_src_sample_planar.g7b" -#include "shaders/render/exa_wm_yuv_rgb.g7b" -#include "shaders/render/exa_wm_write.g7b" +#include "shaders/render/exa_wm_src_affine.g8b" +#include "shaders/render/exa_wm_src_sample_planar.g8b" +#include "shaders/render/exa_wm_yuv_rgb.g8b" +#include "shaders/render/exa_wm_write.g8b" }; static const uint32_t ps_subpic_kernel_static_gen8[][4] = { diff --git a/src/shaders/render/Makefile.am b/src/shaders/render/Makefile.am index bed683b..47d5a6b 100644 --- a/src/shaders/render/Makefile.am +++ b/src/shaders/render/Makefile.am @@ -85,6 +85,20 @@ INTEL_G7B_HASWELL = \ exa_wm_yuv_color_balance.g7b.haswell \ $(NULL) +INTEL_G8A = \ + exa_wm_src_affine.g8a \ + exa_wm_src_sample_planar.g8a \ + exa_wm_write.g8a \ + exa_wm_yuv_rgb.g8a + +INTEL_G8S = $(INTEL_G8A:%.g8a=%.g8s) + +INTEL_G8B = \ + exa_wm_src_affine.g8b \ + exa_wm_src_sample_planar.g8b \ + exa_wm_yuv_rgb.g8b \ + exa_wm_write.g8b + TARGETS = if HAVE_GEN4ASM TARGETS += $(INTEL_G4B) @@ -92,11 +106,12 @@ TARGETS += $(INTEL_G4B_GEN5) TARGETS += $(INTEL_G6B) TARGETS += $(INTEL_G7B) TARGETS += $(INTEL_G7B_HASWELL) +TARGETS += $(INTEL_G8B) endif all-local: $(TARGETS) -SUFFIXES = .g4a .g4s .g4b .g4b.gen5 .g6a .g6s .g6b .g7a .g7s .g7b .g7b.haswell +SUFFIXES = .g4a .g4s .g4b .g4b.gen5 .g6a .g6s .g6b .g7a .g7s .g7b .g7b.haswell .g8a .g8b .g8s if HAVE_GEN4ASM $(INTEL_G4S): $(INTEL_G4A) $(INTEL_G4I) @@ -120,12 +135,21 @@ $(INTEL_G7S): $(INTEL_G7A) $(INTEL_G7I) $(AM_V_GEN)$(GEN4ASM) -g 7 -o $@ $< .g7s.g7b.haswell: $(AM_V_GEN)$(GEN4ASM) -g 7.5 -o $@ $< + + +$(INTEL_G8S): $(INTEL_G8A) $(INTEL_G8I) +.g8a.g8s: + $(AM_V_GEN)m4 $< > $@ +.g8s.g8b: + $(AM_V_GEN)$(GEN4ASM) -g 8 -o $@ $< + endif CLEANFILES = \ $(INTEL_G4S) \ $(INTEL_G6S) \ $(INTEL_G7S) \ + $(INTEL_G8S) \ $(NULL) EXTRA_DIST = \ @@ -138,6 +162,8 @@ EXTRA_DIST = \ $(INTEL_G7A) \ $(INTEL_G7B) \ $(INTEL_G7B_HASWELL) \ + $(INTEL_G8A)) \ + $(INTEL_G8B) \ $(NULL) # Extra clean files so that maintainer-clean removes *everything* diff --git a/src/shaders/render/exa_wm_src_affine.g8a b/src/shaders/render/exa_wm_src_affine.g8a new file mode 100644 index 0000000..1d4efcc --- /dev/null +++ b/src/shaders/render/exa_wm_src_affine.g8a @@ -0,0 +1,47 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +/* + * Fragment to compute src u/v values + */ +include(`exa_wm.g4i') + +define(`ul', `g66') +define(`uh', `g67') +define(`vl', `g68') +define(`vh', `g69') + +define(`bl', `g2.0<8,8,1>F') +define(`bh', `g4.0<8,8,1>F') + +define(`a0_a_x',`g7.0<0,1,0>F') +define(`a0_a_y',`g7.16<0,1,0>F') + +/* U */ +pln (8) ul<1>F a0_a_x bl { align1 }; /* pixel 0-7 */ +pln (8) uh<1>F a0_a_x bh { align1 }; /* pixel 8-15 */ + +/* V */ +pln (8) vl<1>F a0_a_y bl { align1 }; /* pixel 0-7 */ +pln (8) vh<1>F a0_a_y bh { align1 }; /* pixel 8-15 */ diff --git a/src/shaders/render/exa_wm_src_affine.g8b b/src/shaders/render/exa_wm_src_affine.g8b new file mode 100644 index 0000000..0273257 --- /dev/null +++ b/src/shaders/render/exa_wm_src_affine.g8b @@ -0,0 +1,4 @@ + { 0x0060005a, 0x28403ae8, 0x3a0000e0, 0x008d0040 }, + { 0x0060005a, 0x28603ae8, 0x3a0000e0, 0x008d0080 }, + { 0x0060005a, 0x28803ae8, 0x3a0000f0, 0x008d0040 }, + { 0x0060005a, 0x28a03ae8, 0x3a0000f0, 0x008d0080 }, diff --git a/src/shaders/render/exa_wm_src_sample_planar.g8a b/src/shaders/render/exa_wm_src_sample_planar.g8a new file mode 100644 index 0000000..7684491 --- /dev/null +++ b/src/shaders/render/exa_wm_src_sample_planar.g8a @@ -0,0 +1,106 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Wang Zhenyu + * Keith Packard + * Zhao Yakui + */ + +/* Sample the src surface in planar format */ + +include(`exa_wm.g4i') + +/* Ivybridge uses GRFs in SEND instruction */ +define(`src_msg_gen8', `g65') +define(`src_msg_ind_gen8',`65') +/* UV flag */ +define(`uv_flag', `g6.0<0,1,0>UW') + +/* prepare sampler read back gX register, which would be written back to output */ + +/* use simd16 sampler, param 0 is u, param 1 is v. */ +/* 'payload' loading, assuming tex coord start from g4 */ +cmp.e.f0.0 (1) null uv_flag 0x1UW {align1}; +(f0.0) jmpi INTERLEAVED_UV; + +cmp.e.f0.0 (1) null uv_flag 0x2UW {align1}; +(f0.0) jmpi CONSTANT_UV; + +/* load r */ +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* emit sampler 'send' cmd */ + +/* sample U (Cr) */ +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_g<1>UW /* readback */ + null + sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +/* sample V (Cb) */ +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_b<1>UW /* readback */ + null + sampler (5,4,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + +jmpi SAMPLE_Y; + +CONSTANT_UV: +mov (16) src_sample_g<1>f 0.5f { compr align1 mask_disable }; +mov (16) src_sample_b<1>f 0.5f { compr align1 mask_disable }; + +jmpi SAMPLE_Y; + +INTERLEAVED_UV: +mov (1) g0.8<1>UD 0x0000c000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* sample UV (CrCb) */ +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_g<1>UW /* readback */ + null + sampler (3,2,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 4 { align1 }; /* required message len 5, readback len 8 */ + + +SAMPLE_Y: +mov (1) g0.8<1>UD 0x0000e000UD { align1 mask_disable }; +mov (8) src_msg_gen8<1>UD g0<8,8,1>UD { align1 mask_disable }; + +/* sample Y */ +send (16) src_msg_ind_gen8 /* msg reg index */ + src_sample_r<1>UW /* readback */ + null + sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype) + /* here(src->dst) we should use src_sampler and src_surface */ + mlen 5 rlen 2 { align1 }; /* required message len 5, readback len 8 */ + diff --git a/src/shaders/render/exa_wm_src_sample_planar.g8b b/src/shaders/render/exa_wm_src_sample_planar.g8b new file mode 100644 index 0000000..f29cfe4 --- /dev/null +++ b/src/shaders/render/exa_wm_src_sample_planar.g8b @@ -0,0 +1,20 @@ + { 0x01000010, 0x200012e0, 0x160000c0, 0x00010001 }, + { 0x00010020, 0x34000000, 0x0e001400, 0x000000c0 }, + { 0x01000010, 0x200012e0, 0x160000c0, 0x00020002 }, + { 0x00010020, 0x34000000, 0x0e001400, 0x00000070 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22000a48, 0x0e000820, 0x0a2c0203 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22400a48, 0x0e000820, 0x0a2c0405 }, + { 0x00000020, 0x34000000, 0x0e001400, 0x00000060 }, + { 0x00800001, 0x22003eec, 0x38000000, 0x3f000000 }, + { 0x00800001, 0x22403eec, 0x38000000, 0x3f000000 }, + { 0x00000020, 0x34000000, 0x0e001400, 0x00000030 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000c000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x22000a48, 0x0e000820, 0x0a4c0203 }, + { 0x00000001, 0x2008060c, 0x00000000, 0x0000e000 }, + { 0x00600001, 0x2820020c, 0x008d0000, 0x00000000 }, + { 0x02800031, 0x21c00a48, 0x0e000820, 0x0a2c0001 }, diff --git a/src/shaders/render/exa_wm_write.g8a b/src/shaders/render/exa_wm_write.g8a new file mode 100644 index 0000000..58347b3 --- /dev/null +++ b/src/shaders/render/exa_wm_write.g8a @@ -0,0 +1,83 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +include(`exa_wm.g4i') + +/* header */ +define(`data_port_msg_2_0', `g64') +define(`data_port_msg_2_1', `g65') +define(`data_port_msg_2_ind', `64') + +mov (8) data_port_msg_2_0<1>UD g0<8,8,1>UD {align1 mask_disable}; +mov (8) data_port_msg_2_1<1>UD g1<8,8,1>UD {align1 mask_disable}; + +/* + * Prepare data in g66-g67 for Red channel, g68-g69 for Green channel, + * g70-g71 for Blue and g72-g73 for Alpha channel + */ +define(`slot_r_00', `g66') +define(`slot_r_01', `g67') +define(`slot_g_00', `g68') +define(`slot_g_01', `g69') +define(`slot_b_00', `g70') +define(`slot_b_01', `g71') +define(`slot_a_00', `g72') +define(`slot_a_01', `g73') + +mov (8) slot_r_00<1>F src_sample_r_01<1>F { align1 mask_disable }; +mov (8) slot_r_01<1>F src_sample_r_23<1>F { align1 mask_disable }; + +mov (8) slot_g_00<1>F src_sample_g_01<1>F { align1 mask_disable }; +mov (8) slot_g_01<1>F src_sample_g_23<1>F { align1 mask_disable }; + +mov (8) slot_b_00<1>F src_sample_b_01<1>F { align1 mask_disable }; +mov (8) slot_b_01<1>F src_sample_b_23<1>F { align1 mask_disable }; + +mov (8) slot_a_00<1>F src_sample_a_01<1>F { align1 mask_disable }; +mov (8) slot_a_01<1>F src_sample_a_23<1>F { align1 mask_disable }; + +send (16) + data_port_msg_2_ind + null<1>UW + null + write ( + 0, /* binding table index */ + 16, /* last render target(1) + slots 15:0(0) + msg type simd16 single source(000) */ + 12, /* render target write */ + 0, /* ignore for Ivybridge */ + 1 /* header present */ + ) + mlen 10 + rlen 0 + { align1 EOT }; + +nop; +nop; +nop; +nop; +nop; +nop; +nop; +nop; + diff --git a/src/shaders/render/exa_wm_write.g8b b/src/shaders/render/exa_wm_write.g8b new file mode 100644 index 0000000..2f237de --- /dev/null +++ b/src/shaders/render/exa_wm_write.g8b @@ -0,0 +1,19 @@ + { 0x00600001, 0x2800020c, 0x008d0000, 0x00000000 }, + { 0x00600001, 0x2820020c, 0x008d0020, 0x00000000 }, + { 0x00600001, 0x28403aec, 0x002001c0, 0x00000000 }, + { 0x00600001, 0x28603aec, 0x002001e0, 0x00000000 }, + { 0x00600001, 0x28803aec, 0x00200200, 0x00000000 }, + { 0x00600001, 0x28a03aec, 0x00200220, 0x00000000 }, + { 0x00600001, 0x28c03aec, 0x00200240, 0x00000000 }, + { 0x00600001, 0x28e03aec, 0x00200260, 0x00000000 }, + { 0x00600001, 0x29003aec, 0x00200280, 0x00000000 }, + { 0x00600001, 0x29203aec, 0x002002a0, 0x00000000 }, + { 0x05800031, 0x20000a40, 0x0e000800, 0x940b1000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, + { 0x0000007e, 0x00000000, 0x00000000, 0x00000000 }, diff --git a/src/shaders/render/exa_wm_yuv_rgb.g8a b/src/shaders/render/exa_wm_yuv_rgb.g8a new file mode 100644 index 0000000..62669c8 --- /dev/null +++ b/src/shaders/render/exa_wm_yuv_rgb.g8a @@ -0,0 +1,106 @@ +/* + * Copyright © 2013 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Keith Packard + * Eric Anholt + * Zhao Yakui + * + */ + +include(`exa_wm.g4i') + +define(`YCbCr_base', `src_sample_base') + +define(`Cr', `src_sample_b') +define(`Cr_01', `src_sample_b_01') +define(`Cr_23', `src_sample_b_23') + +define(`Y', `src_sample_r') +define(`Y_01', `src_sample_r_01') +define(`Y_23', `src_sample_r_23') + +define(`Cb', `src_sample_g') +define(`Cb_01', `src_sample_g_01') +define(`Cb_23', `src_sample_g_23') + +define(`Crn', `mask_sample_g') +define(`Crn_01', `mask_sample_g_01') +define(`Crn_23', `mask_sample_g_23') + +define(`Yn', `mask_sample_r') +define(`Yn_01', `mask_sample_r_01') +define(`Yn_23', `mask_sample_r_23') + +define(`Cbn', `mask_sample_b') +define(`Cbn_01', `mask_sample_b_01') +define(`Cbn_23', `mask_sample_b_23') + + /* color space conversion function: + * R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1) + * G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1) + * B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1) + */ + + /* Normalize Y, Cb and Cr: + * + * Yn = (Y - 16/255) * 1.164 + * Crn = Cr - 128 / 255 + * Cbn = Cb - 128 / 255 + */ +add (16) Yn<1>F Y<8;8,1>F -0.0627451F { compr align1 }; +mul (16) Yn<1>F Yn<8;8,1>F 1.164F { compr align1 }; + +add (16) Crn<1>F Cr<8;8,1>F -0.501961F { compr align1 }; + +add (16) Cbn<1>F Cb<8;8,1>F -0.501961F { compr align1 }; + + /* + * R = Y + Cr * 1.596 + */ +mov (8) acc0<1>F Yn_01.0<8;8,1>F { align1 }; +mac.sat(8) src_sample_r_01<1>F Crn_01<8;8,1>F 1.596F { align1 }; +mov (8) acc0<1>F Yn_23.0<8;8,1>F { align1 }; +mac.sat(8) src_sample_r_23<1>F Crn_23<8;8,1>F 1.596F { align1 }; + + /* + * G = Crn * -0.813 + Cbn * -0.392 + Y + */ +mov (8) acc0<1>F Yn_01.0<8;8,1>F { align1 }; +mac (8) acc0<1>F Crn_01.0<8;8,1>F -0.813F { align1 }; +mac.sat(8) src_sample_g_01<1>F Cbn_01.0<8;8,1>F -0.392F { align1 }; +mov (8) acc0<1>F Yn_23.0<8;8,1>F { align1 }; +mac (8) acc0<1>F Crn_23.0<8;8,1>F -0.813F { align1 }; +mac.sat(8) src_sample_g_23<1>F Cbn_23.0<8;8,1>F -0.392F { align1 }; + + /* + * B = Cbn * 2.017 + Y + */ +mov (8) acc0<1>F Yn_01.0<8;8,1>F { align1 }; +mac.sat(8) src_sample_b_01<1>F Cbn_01.0<8;8,1>F 2.017F { align1 }; + +mov (8) acc0<1>F Yn_23.0<8;8,1>F { align1 }; +mac.sat(8) src_sample_b_23<1>F Cbn_23.0<8;8,1>F 2.017F { align1 }; + /* + * A = 1.0 + */ +mov (16) src_sample_a<1>F 1.0F { compr align1 }; diff --git a/src/shaders/render/exa_wm_yuv_rgb.g8b b/src/shaders/render/exa_wm_yuv_rgb.g8b new file mode 100644 index 0000000..8898a39 --- /dev/null +++ b/src/shaders/render/exa_wm_yuv_rgb.g8b @@ -0,0 +1,19 @@ + { 0x00800040, 0x22c03ae8, 0x3e8d01c0, 0xbd808081 }, + { 0x00800041, 0x22c03ae8, 0x3e8d02c0, 0x3f94fdf4 }, + { 0x00800040, 0x23003ae8, 0x3e8d0240, 0xbf008084 }, + { 0x00800040, 0x23403ae8, 0x3e8d0200, 0xbf008084 }, + { 0x00600001, 0x24003ae0, 0x008d02c0, 0x00000000 }, + { 0x80600048, 0x21c03ae8, 0x3e8d0300, 0x3fcc49ba }, + { 0x00600001, 0x24003ae0, 0x008d02e0, 0x00000000 }, + { 0x80600048, 0x21e03ae8, 0x3e8d0320, 0x3fcc49ba }, + { 0x00600001, 0x24003ae0, 0x008d02c0, 0x00000000 }, + { 0x00600048, 0x24003ae0, 0x3e8d0300, 0xbf5020c5 }, + { 0x80600048, 0x22003ae8, 0x3e8d0340, 0xbec8b439 }, + { 0x00600001, 0x24003ae0, 0x008d02e0, 0x00000000 }, + { 0x00600048, 0x24003ae0, 0x3e8d0320, 0xbf5020c5 }, + { 0x80600048, 0x22203ae8, 0x3e8d0360, 0xbec8b439 }, + { 0x00600001, 0x24003ae0, 0x008d02c0, 0x00000000 }, + { 0x80600048, 0x22403ae8, 0x3e8d0340, 0x40011687 }, + { 0x00600001, 0x24003ae0, 0x008d02e0, 0x00000000 }, + { 0x80600048, 0x22603ae8, 0x3e8d0360, 0x40011687 }, + { 0x00800001, 0x22803ee8, 0x38000000, 0x3f800000 }, -- 2.7.4