From 411d9ed4486a4e40bded42b2e026ba3ce866891f Mon Sep 17 00:00:00 2001 From: Tomasz Figa Date: Wed, 1 May 2013 21:02:28 +0200 Subject: [PATCH] drm/exynos: fimd: Add support for FIMD variants with clock selection Some platforms that can be supported this driver has additional clock source selection bits in VIDCON0 register that allows to select which clock should be used to drive the pixel clock: bus clock or special clock. Since this driver assumes that special clock always drives the pixel clock, this patch sets the selection bitfield to use the special clock. Signed-off-by: Tomasz Figa Acked-by: Joonyoung Shim Signed-off-by: Inki Dae --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 015a3be..7681a8a 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -65,6 +65,7 @@ struct fimd_driver_data { unsigned int timing_base; unsigned int has_shadowcon:1; + unsigned int has_clksel:1; }; static struct fimd_driver_data exynos4_fimd_driver_data = { @@ -278,6 +279,11 @@ static void fimd_commit(struct device *dev) val = ctx->vidcon0; val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); + if (ctx->driver_data->has_clksel) { + val &= ~VIDCON0_CLKSEL_MASK; + val |= VIDCON0_CLKSEL_LCD; + } + if (ctx->clkdiv > 1) val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; else -- 2.7.4