From 40e4a59dfd1ac39990fabc4bd08e341a2d7644e3 Mon Sep 17 00:00:00 2001 From: nemet Date: Thu, 10 Apr 2008 18:28:45 +0000 Subject: [PATCH] * config/mips/mips.md (GPR2): New mode iterator. (seq): Add comment. (*seq_, *seq__mips16, *sne_, *sgt_, *sgt__mips16, *sge_, *slt_, *slt__mips16 *sle_, *sle__mips16): Rewrite these to take two modes, the mode of comparison and the mode of the destination. * config/mips/mips.c (mips_expand_scc): Instead of having paradoxical subreg as destination, expand "narrowing" scc if mode of comparison is SI and target is requested in DI mode. (mips_emit_int_order_test): Update comment. Make mode of comparison match CMP0 rather than TARGET. When creating inverse target use mode of TARGET. testsuite/ * gcc.target/mips/scc-2.c: New test. * gcc.target/mips/scc-3.c: New test. * gcc.target/mips/scc-4.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@134167 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 16 +++++ gcc/config/mips/mips.c | 13 ++--- gcc/config/mips/mips.md | 106 ++++++++++++++++++---------------- gcc/testsuite/ChangeLog | 6 ++ gcc/testsuite/gcc.target/mips/scc-2.c | 17 ++++++ gcc/testsuite/gcc.target/mips/scc-3.c | 17 ++++++ gcc/testsuite/gcc.target/mips/scc-4.c | 13 +++++ 7 files changed, 131 insertions(+), 57 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/scc-2.c create mode 100644 gcc/testsuite/gcc.target/mips/scc-3.c create mode 100644 gcc/testsuite/gcc.target/mips/scc-4.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ba6a33f..d259935 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,21 @@ 2008-04-10 Adam Nemet + * config/mips/mips.md (GPR2): New mode iterator. + (seq): Add comment. + (*seq_, *seq__mips16, *sne_, *sgt_, + *sgt__mips16, *sge_, *slt_, + *slt__mips16 *sle_, *sle__mips16): + Rewrite these to take two modes, the mode of comparison and the + mode of the destination. + * config/mips/mips.c (mips_expand_scc): Instead of having + paradoxical subreg as destination, expand "narrowing" scc if mode + of comparison is SI and target is requested in DI mode. + (mips_emit_int_order_test): Update comment. Make mode of + comparison match CMP0 rather than TARGET. When creating inverse + target use mode of TARGET. + +2008-04-10 Adam Nemet + * gcov-dump.c (tag_summary): Only print summaries for the first GCOV_COUNTERS_SUMMABLE counters. diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index b9c4950..d69169f 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -3715,9 +3715,9 @@ mips_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, } /* Compare CMP0 and CMP1 using ordering test CODE and store the result - in TARGET. CMP0 and TARGET are register_operands that have the same - integer mode. If INVERT_PTR is nonnull, it's OK to set TARGET to the - inverse of the result and flip *INVERT_PTR instead. */ + in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR + is nonnull, it's OK to set TARGET to the inverse of the result and + flip *INVERT_PTR instead. */ static void mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, @@ -3728,7 +3728,7 @@ mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, /* First see if there is a MIPS instruction that can do this operation. If not, try doing the same for the inverse operation. If that also fails, force CMP1 into a register and try again. */ - mode = GET_MODE (target); + mode = GET_MODE (cmp0); if (mips_canonicalize_int_order_test (&code, &cmp1, mode)) mips_emit_binary (code, target, cmp0, cmp1); else @@ -3741,7 +3741,7 @@ mips_emit_int_order_test (enum rtx_code code, bool *invert_ptr, } else if (invert_ptr == 0) { - rtx inv_target = gen_reg_rtx (mode); + rtx inv_target = gen_reg_rtx (GET_MODE (target)); mips_emit_binary (inv_code, inv_target, cmp0, cmp1); mips_emit_binary (XOR, target, inv_target, const1_rtx); } @@ -3868,7 +3868,7 @@ mips_emit_compare (enum rtx_code *code, rtx *op0, rtx *op1, bool need_eq_ne_p) /* Try comparing cmp_operands[0] and cmp_operands[1] using rtl code CODE. Store the result in TARGET and return true if successful. - On 64-bit targets, TARGET may be wider than cmp_operands[0]. */ + On 64-bit targets, TARGET may be narrower than cmp_operands[0]. */ bool mips_expand_scc (enum rtx_code code, rtx target) @@ -3876,7 +3876,6 @@ mips_expand_scc (enum rtx_code code, rtx target) if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) != MODE_INT) return false; - target = gen_lowpart (GET_MODE (cmp_operands[0]), target); if (code == EQ || code == NE) { rtx zie = mips_zero_if_equal (cmp_operands[0], cmp_operands[1]); diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 2083cb9..cbdcdc6 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -476,6 +476,10 @@ ;; from the same template. (define_mode_iterator GPR [SI (DI "TARGET_64BIT")]) +;; A copy of GPR that can be used when a pattern has two independent +;; modes. +(define_mode_iterator GPR2 [SI (DI "TARGET_64BIT")]) + ;; This mode iterator allows :P to be used for patterns that operate on ;; pointer-sized quantities. Exactly one of the two alternatives will match. (define_mode_iterator P [(SI "Pmode == SImode") (DI "Pmode == DImode")]) @@ -5065,6 +5069,8 @@ ;; ;; .................... +;; Destination is always set in SI mode. + (define_expand "seq" [(set (match_operand:SI 0 "register_operand") (eq:SI (match_dup 1) @@ -5072,23 +5078,23 @@ "" { if (mips_expand_scc (EQ, operands[0])) DONE; else FAIL; }) -(define_insn "*seq_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (eq:GPR (match_operand:GPR 1 "register_operand" "d") - (const_int 0)))] +(define_insn "*seq_" + [(set (match_operand:GPR2 0 "register_operand" "=d") + (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") + (const_int 0)))] "!TARGET_MIPS16" "sltu\t%0,%1,1" [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -(define_insn "*seq__mips16" - [(set (match_operand:GPR 0 "register_operand" "=t") - (eq:GPR (match_operand:GPR 1 "register_operand" "d") - (const_int 0)))] +(define_insn "*seq__mips16" + [(set (match_operand:GPR2 0 "register_operand" "=t") + (eq:GPR2 (match_operand:GPR 1 "register_operand" "d") + (const_int 0)))] "TARGET_MIPS16" "sltu\t%1,1" [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) ;; "sne" uses sltu instructions in which the first operand is $0. ;; This isn't possible in mips16 code. @@ -5100,14 +5106,14 @@ "!TARGET_MIPS16" { if (mips_expand_scc (NE, operands[0])) DONE; else FAIL; }) -(define_insn "*sne_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (ne:GPR (match_operand:GPR 1 "register_operand" "d") - (const_int 0)))] +(define_insn "*sne_" + [(set (match_operand:GPR2 0 "register_operand" "=d") + (ne:GPR2 (match_operand:GPR 1 "register_operand" "d") + (const_int 0)))] "!TARGET_MIPS16" "sltu\t%0,%.,%1" [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_expand "sgt" [(set (match_operand:SI 0 "register_operand") @@ -5116,23 +5122,23 @@ "" { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*sgt_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (any_gt:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] +(define_insn "*sgt_" + [(set (match_operand:GPR2 0 "register_operand" "=d") + (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "reg_or_0_operand" "dJ")))] "!TARGET_MIPS16" "slt\t%0,%z2,%1" [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -(define_insn "*sgt__mips16" - [(set (match_operand:GPR 0 "register_operand" "=t") - (any_gt:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "register_operand" "d")))] +(define_insn "*sgt__mips16" + [(set (match_operand:GPR2 0 "register_operand" "=t") + (any_gt:GPR2 (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "register_operand" "d")))] "TARGET_MIPS16" "slt\t%2,%1" [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_expand "sge" [(set (match_operand:SI 0 "register_operand") @@ -5141,14 +5147,14 @@ "" { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*sge_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (any_ge:GPR (match_operand:GPR 1 "register_operand" "d") - (const_int 1)))] +(define_insn "*sge_" + [(set (match_operand:GPR2 0 "register_operand" "=d") + (any_ge:GPR2 (match_operand:GPR 1 "register_operand" "d") + (const_int 1)))] "!TARGET_MIPS16" "slt\t%0,%.,%1" [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) (define_expand "slt" [(set (match_operand:SI 0 "register_operand") @@ -5157,23 +5163,23 @@ "" { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*slt_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (any_lt:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "arith_operand" "dI")))] +(define_insn "*slt_" + [(set (match_operand:GPR2 0 "register_operand" "=d") + (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "arith_operand" "dI")))] "!TARGET_MIPS16" "slt\t%0,%1,%2" [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -(define_insn "*slt__mips16" - [(set (match_operand:GPR 0 "register_operand" "=t,t") - (any_lt:GPR (match_operand:GPR 1 "register_operand" "d,d") - (match_operand:GPR 2 "arith_operand" "d,I")))] +(define_insn "*slt__mips16" + [(set (match_operand:GPR2 0 "register_operand" "=t,t") + (any_lt:GPR2 (match_operand:GPR 1 "register_operand" "d,d") + (match_operand:GPR 2 "arith_operand" "d,I")))] "TARGET_MIPS16" "slt\t%1,%2" [(set_attr "type" "slt") - (set_attr "mode" "") + (set_attr "mode" "") (set_attr_alternative "length" [(const_int 4) (if_then_else (match_operand 2 "m16_uimm8_1") @@ -5187,29 +5193,29 @@ "" { if (mips_expand_scc (, operands[0])) DONE; else FAIL; }) -(define_insn "*sle_" - [(set (match_operand:GPR 0 "register_operand" "=d") - (any_le:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "sle_operand" "")))] +(define_insn "*sle_" + [(set (match_operand:GPR2 0 "register_operand" "=d") + (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "sle_operand" "")))] "!TARGET_MIPS16" { operands[2] = GEN_INT (INTVAL (operands[2]) + 1); return "slt\t%0,%1,%2"; } [(set_attr "type" "slt") - (set_attr "mode" "")]) + (set_attr "mode" "")]) -(define_insn "*sle__mips16" - [(set (match_operand:GPR 0 "register_operand" "=t") - (any_le:GPR (match_operand:GPR 1 "register_operand" "d") - (match_operand:GPR 2 "sle_operand" "")))] +(define_insn "*sle__mips16" + [(set (match_operand:GPR2 0 "register_operand" "=t") + (any_le:GPR2 (match_operand:GPR 1 "register_operand" "d") + (match_operand:GPR 2 "sle_operand" "")))] "TARGET_MIPS16" { operands[2] = GEN_INT (INTVAL (operands[2]) + 1); return "slt\t%1,%2"; } [(set_attr "type" "slt") - (set_attr "mode" "") + (set_attr "mode" "") (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1") (const_int 4) (const_int 8)))]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 1eab06b..b22bcd4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,9 @@ +2008-04-10 Adam Nemet + + * gcc.target/mips/scc-2.c: New test. + * gcc.target/mips/scc-3.c: New test. + * gcc.target/mips/scc-4.c: New test. + 2008-04-10 Ira Rosen PR tree-optimization/35821 diff --git a/gcc/testsuite/gcc.target/mips/scc-2.c b/gcc/testsuite/gcc.target/mips/scc-2.c new file mode 100644 index 0000000..7964227 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/scc-2.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-O -mgp64" } */ + +/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */ +/* { dg-final { scan-assembler-times "slt\t\|sltu\t" 12 } } */ + + +#define TEST(N, LHS, REL, RHS) \ + NOMIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \ + NOMIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \ + +TEST (eq, a, ==, 0); +TEST (ne, a, !=, 0); +TEST (gt, a, >, b); +TEST (ge, a, >=, 1); +TEST (lt, a, <, b); +TEST (le, a, <=, 11); diff --git a/gcc/testsuite/gcc.target/mips/scc-3.c b/gcc/testsuite/gcc.target/mips/scc-3.c new file mode 100644 index 0000000..e496d40 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/scc-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-O -mabi=o64" } */ + +/* { dg-final { scan-assembler-not "and\t\|andi\t\|ext\t\|sll\t\|srl\t" } } */ +/* { dg-final { scan-assembler-times "slt\t\|sltu\t" 8 } } */ + + +#define TEST(N, LHS, REL, RHS) \ + MIPS16 long long w##N (int a, int b) {return LHS REL RHS;} \ + MIPS16 int n##N (long long a, long long b) {return LHS REL RHS;} \ + +TEST (eq, a, ==, 0); + +TEST (gt, a, >, b); + +TEST (lt, a, <, b); +TEST (le, a, <=, 11); diff --git a/gcc/testsuite/gcc.target/mips/scc-4.c b/gcc/testsuite/gcc.target/mips/scc-4.c new file mode 100644 index 0000000..fd6e932 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/scc-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-mips-options "-O -mabi=o64" } */ + +/* { dg-final { scan-assembler "slt\t" } } */ +/* { dg-final { scan-assembler "sltu\t\|xor\t\|xori\t" } } */ + +/* This test should work both in mips16 and non-mips16 mode. */ + +int +f (long long a, long long b) +{ + return a > 5; +} -- 2.7.4