From 401bdd7d1e938272065511be94431f16f12448e3 Mon Sep 17 00:00:00 2001 From: M Henning Date: Thu, 3 Aug 2023 22:58:22 -0400 Subject: [PATCH] nv/codegen: Delete OP_WRSV It's never generated by anything. Reviewed-by: Karol Herbst Part-of: --- src/nouveau/codegen/nv50_ir.h | 1 - src/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 20 -------------------- src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 23 ----------------------- src/nouveau/codegen/nv50_ir_lowering_nvc0.h | 1 - src/nouveau/codegen/nv50_ir_peephole.cpp | 3 +-- src/nouveau/codegen/nv50_ir_print.cpp | 1 - src/nouveau/codegen/nv50_ir_target.cpp | 6 +++--- src/nouveau/codegen/nv50_ir_target_nv50.cpp | 2 +- src/nouveau/codegen/nv50_ir_target_nvc0.cpp | 2 +- 9 files changed, 6 insertions(+), 53 deletions(-) diff --git a/src/nouveau/codegen/nv50_ir.h b/src/nouveau/codegen/nv50_ir.h index 940e084..09a3ae0 100644 --- a/src/nouveau/codegen/nv50_ir.h +++ b/src/nouveau/codegen/nv50_ir.h @@ -144,7 +144,6 @@ enum operation OP_DFDX, OP_DFDY, OP_RDSV, // read system value - OP_WRSV, // write system value OP_PIXLD, // get info about raster object or surfaces OP_QUADOP, OP_QUADON, diff --git a/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp b/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp index a3e44b4..78f76cf 100644 --- a/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp +++ b/src/nouveau/codegen/nv50_ir_lowering_nv50.cpp @@ -641,7 +641,6 @@ private: virtual bool visit(Function *); bool handleRDSV(Instruction *); - bool handleWRSV(Instruction *); bool handlePFETCH(Instruction *); bool handleEXPORT(Instruction *); @@ -1226,23 +1225,6 @@ NV50LoweringPreSSA::handleSELP(Instruction *i) } bool -NV50LoweringPreSSA::handleWRSV(Instruction *i) -{ - Symbol *sym = i->getSrc(0)->asSym(); - - // these are all shader outputs, $sreg are not writeable - uint32_t addr = targ->getSVAddress(FILE_SHADER_OUTPUT, sym); - if (addr >= 0x400) - return false; - sym = bld.mkSymbol(FILE_SHADER_OUTPUT, 0, i->sType, addr); - - bld.mkStore(OP_EXPORT, i->dType, sym, i->getIndirect(0, 0), i->getSrc(1)); - - bld.getBB()->remove(i); - return true; -} - -bool NV50LoweringPreSSA::handleCALL(Instruction *i) { if (prog->getType() == Program::TYPE_COMPUTE) { @@ -2223,8 +2205,6 @@ NV50LoweringPreSSA::visit(Instruction *i) return handleBUFQ(i); case OP_RDSV: return handleRDSV(i); - case OP_WRSV: - return handleWRSV(i); case OP_CALL: return handleCALL(i); case OP_PRECONT: diff --git a/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp index 486bb26..963a8d7 100644 --- a/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp +++ b/src/nouveau/codegen/nv50_ir_lowering_nvc0.cpp @@ -2801,27 +2801,6 @@ NVC0LoweringPass::handleSurfaceOpGM107(TexInstruction *su) } } -bool -NVC0LoweringPass::handleWRSV(Instruction *i) -{ - Instruction *st; - Symbol *sym; - uint32_t addr; - - // must replace, $sreg are not writeable - addr = targ->getSVAddress(FILE_SHADER_OUTPUT, i->getSrc(0)->asSym()); - if (addr >= 0x400) - return false; - sym = bld.mkSymbol(FILE_SHADER_OUTPUT, 0, i->sType, addr); - - st = bld.mkStore(OP_EXPORT, i->dType, sym, i->getIndirect(0, 0), - i->getSrc(1)); - st->perPatch = i->perPatch; - - bld.getBB()->remove(i); - return true; -} - void NVC0LoweringPass::handleLDST(Instruction *i) { @@ -3362,8 +3341,6 @@ NVC0LoweringPass::visit(Instruction *i) return handleOUT(i); case OP_RDSV: return handleRDSV(i); - case OP_WRSV: - return handleWRSV(i); case OP_STORE: case OP_LOAD: handleLDST(i); diff --git a/src/nouveau/codegen/nv50_ir_lowering_nvc0.h b/src/nouveau/codegen/nv50_ir_lowering_nvc0.h index 17c944a..227dcbc 100644 --- a/src/nouveau/codegen/nv50_ir_lowering_nvc0.h +++ b/src/nouveau/codegen/nv50_ir_lowering_nvc0.h @@ -129,7 +129,6 @@ public: protected: bool handleRDSV(Instruction *); - bool handleWRSV(Instruction *); bool handleEXPORT(Instruction *); bool handleOUT(Instruction *); bool handleDIV(Instruction *); diff --git a/src/nouveau/codegen/nv50_ir_peephole.cpp b/src/nouveau/codegen/nv50_ir_peephole.cpp index 4193740..d066354 100644 --- a/src/nouveau/codegen/nv50_ir_peephole.cpp +++ b/src/nouveau/codegen/nv50_ir_peephole.cpp @@ -66,8 +66,7 @@ bool Instruction::isDead() const if (op == OP_STORE || op == OP_EXPORT || op == OP_ATOM || - op == OP_SUSTB || op == OP_SUSTP || op == OP_SUREDP || op == OP_SUREDB || - op == OP_WRSV) + op == OP_SUSTB || op == OP_SUSTP || op == OP_SUREDP || op == OP_SUREDB) return false; for (int d = 0; defExists(d); ++d) diff --git a/src/nouveau/codegen/nv50_ir_print.cpp b/src/nouveau/codegen/nv50_ir_print.cpp index bd7a828..3b2843e 100644 --- a/src/nouveau/codegen/nv50_ir_print.cpp +++ b/src/nouveau/codegen/nv50_ir_print.cpp @@ -171,7 +171,6 @@ const char *operationStr[OP_LAST + 1] = "dfdx", "dfdy", "rdsv", - "wrsv", "pixld", "quadop", "quadon", diff --git a/src/nouveau/codegen/nv50_ir_target.cpp b/src/nouveau/codegen/nv50_ir_target.cpp index c65eceb..a85bce9 100644 --- a/src/nouveau/codegen/nv50_ir_target.cpp +++ b/src/nouveau/codegen/nv50_ir_target.cpp @@ -50,7 +50,7 @@ const uint8_t Target::operationSrcNr[] = 3, 3, 3, 1, 3, // SUBFM, SUCLAMP, SUEAU, SUQ, MADSP 0, // TEXBAR 1, 1, // DFDX, DFDY - 1, 2, 1, 2, 0, 0, // RDSV, WRSV, PIXLD, QUADOP, QUADON, QUADPOP + 1, 1, 2, 0, 0, // RDSV, PIXLD, QUADOP, QUADON, QUADPOP 2, 3, 2, 1, 1, 2, 3, // POPCNT, INSBF, EXTBF, BFIND, BREV, BMSK, PERMT 2, // SGXT 3, 2, // ATOM, BAR @@ -118,8 +118,8 @@ const OpClass Target::operationClass[] = OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_ARITH, // TEXBAR OPCLASS_OTHER, - // DFDX, DFDY, RDSV, WRSV; PIXLD, QUADOP, QUADON, QUADPOP - OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, + // DFDX, DFDY, RDSV; PIXLD, QUADOP, QUADON, QUADPOP + OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_OTHER, OPCLASS_CONTROL, OPCLASS_CONTROL, // POPCNT, INSBF, EXTBF, BFIND, BREV, BMSK; PERMT, SGXT OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD, OPCLASS_BITFIELD, diff --git a/src/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/nouveau/codegen/nv50_ir_target_nv50.cpp index 4bbef49..666691e 100644 --- a/src/nouveau/codegen/nv50_ir_target_nv50.cpp +++ b/src/nouveau/codegen/nv50_ir_target_nv50.cpp @@ -123,7 +123,7 @@ void TargetNV50::initOpInfo() }; static const operation noDestList[] = { - OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT, + OP_STORE, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT, OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET, OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART, OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP, diff --git a/src/nouveau/codegen/nv50_ir_target_nvc0.cpp b/src/nouveau/codegen/nv50_ir_target_nvc0.cpp index beeac75..37cea5d 100644 --- a/src/nouveau/codegen/nv50_ir_target_nvc0.cpp +++ b/src/nouveau/codegen/nv50_ir_target_nvc0.cpp @@ -206,7 +206,7 @@ void TargetNVC0::initOpInfo() static const operation noDest[] = { - OP_STORE, OP_WRSV, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT, + OP_STORE, OP_EXPORT, OP_BRA, OP_CALL, OP_RET, OP_EXIT, OP_DISCARD, OP_CONT, OP_BREAK, OP_PRECONT, OP_PREBREAK, OP_PRERET, OP_JOIN, OP_JOINAT, OP_BRKPT, OP_MEMBAR, OP_EMIT, OP_RESTART, OP_QUADON, OP_QUADPOP, OP_TEXBAR, OP_SUSTB, OP_SUSTP, OP_SUREDP, -- 2.7.4