From 4006e09d1d0e910e1379718ba38a9a052b86b852 Mon Sep 17 00:00:00 2001 From: Ulrich Weigand Date: Tue, 8 Nov 2016 20:17:02 +0000 Subject: [PATCH] [SystemZ] Add program mask and addressing mode instructions Add several instructions that operate on the program mask or the addressing mode. These are not really needed for code generation under Linux, but are provided for completeness for the assembler/disassembler. llvm-svn: 286284 --- llvm/lib/Target/SystemZ/SystemZInstrFormats.td | 7 +++ llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 39 +++++++++++-- llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 26 ++++++++- llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 22 +++++++- llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 26 ++++++++- llvm/test/MC/Disassembler/SystemZ/insns.txt | 75 +++++++++++++++++++++++++ llvm/test/MC/SystemZ/insn-bad.s | 8 +++ llvm/test/MC/SystemZ/insn-good.s | 64 +++++++++++++++++++++ 8 files changed, 256 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td index ca4f837..8671db6 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td @@ -2116,6 +2116,13 @@ class SideEffectUnaryI opcode, Immediate imm> let hasSideEffects = 1; } +class SideEffectUnaryRRopcode, RegisterOperand cls> + : InstRR { + let hasSideEffects = 1; + let R2 = 0; +} + class SideEffectUnaryS opcode, SDPatternOperator operator> : InstS; defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; //===----------------------------------------------------------------------===// +// Program mask and addressing mode +//===----------------------------------------------------------------------===// + +// Extract CC and program mask into a register. CC ends up in bits 29 and 28. +let Uses = [CC] in + def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; + +// Set CC and program mask from a register. +let Defs = [CC] in + def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; + +// Branch and link - like BAS, but also extracts CC and program mask. +let isCall = 1, Uses = [CC], Defs = [CC] in { + def BAL : CallRX<"bal", 0x45>; + def BALR : CallRR<"balr", 0x05>; +} + +// Test addressing mode. +let Defs = [CC] in + def TAM : SideEffectInherentE<"tam", 0x010B>; + +// Set addressing mode. +def SAM24 : SideEffectInherentE<"sam24", 0x010C>; +def SAM31 : SideEffectInherentE<"sam31", 0x010D>; +def SAM64 : SideEffectInherentE<"sam64", 0x010E>; + +// Branch and set mode. Not really a call, but also sets an output register. +let isBranch = 1, isTerminator = 1, isBarrier = 1 in + def BSM : CallRR<"bsm", 0x0B>; + +// Branch and save and set mode. +let isCall = 1, Defs = [CC] in + def BASSM : CallRR<"bassm", 0x0C>; + +//===----------------------------------------------------------------------===// // Transactional execution //===----------------------------------------------------------------------===// @@ -1507,10 +1542,6 @@ let Predicates = [FeatureProcessorAssist] in { // Miscellaneous Instructions. //===----------------------------------------------------------------------===// -// Extract CC into bits 29 and 28 of a register. -let Uses = [CC] in - def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; - // Find leftmost one, AKA count leading zeros. The instruction actually // returns a pair of GR64s, the first giving the number of leading zeros // and the second giving a copy of the source with the leftmost one bit diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td index 6857af5..11ceca1 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ13.td @@ -533,6 +533,29 @@ def : InstRW<[LSU, FXa], (instregex "LAE(Y)?$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>; //===----------------------------------------------------------------------===// +// Program mask and addressing mode +//===----------------------------------------------------------------------===// + +// Insert Program Mask +def : InstRW<[FXa, Lat3, EndGroup], (instregex "IPM$")>; + +// Set Program Mask +def : InstRW<[LSU, EndGroup], (instregex "SPM$")>; + +// Branch and link +def : InstRW<[FXa, FXa, FXb, Lat5, GroupAlone], (instregex "BAL(R)?$")>; + +// Test addressing mode +def : InstRW<[FXb, EndGroup], (instregex "TAM$")>; + +// Set addressing mode +def : InstRW<[FXb, FXb, Lat2, EndGroup], (instregex "SAM(24|31|64)$")>; + +// Branch (and save) and set mode. +def : InstRW<[FXa, FXb, Lat2, GroupAlone], (instregex "BSM$")>; +def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "BASSM$")>; + +//===----------------------------------------------------------------------===// // Transactional execution //===----------------------------------------------------------------------===// @@ -562,9 +585,6 @@ def : InstRW<[FXb], (instregex "PPA$")>; // Miscellaneous Instructions. //===----------------------------------------------------------------------===// -// Insert Program Mask -def : InstRW<[FXa, Lat3, EndGroup], (instregex "IPM$")>; - // Find leftmost one def : InstRW<[FXa, Lat6, GroupAlone], (instregex "FLOGR$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td index d964865..d7022fb 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZ196.td @@ -510,12 +510,32 @@ def : InstRW<[LSU, FXU], (instregex "LAE(Y)?$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>; //===----------------------------------------------------------------------===// -// Miscellaneous Instructions. +// Program mask and addressing mode //===----------------------------------------------------------------------===// // Insert Program Mask def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>; +// Set Program Mask +def : InstRW<[LSU, EndGroup], (instregex "SPM$")>; + +// Branch and link +def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>; + +// Test addressing mode +def : InstRW<[FXU, EndGroup], (instregex "TAM$")>; + +// Set addressing mode +def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>; + +// Branch (and save) and set mode. +def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "BSM$")>; +def : InstRW<[FXU, FXU, LSU, Lat5, GroupAlone], (instregex "BASSM$")>; + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +//===----------------------------------------------------------------------===// + // Find leftmost one def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>; diff --git a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td index 0f005f4..fb1c17e 100644 --- a/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td +++ b/llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td @@ -512,6 +512,29 @@ def : InstRW<[LSU, FXU], (instregex "LAE(Y)?$")>; def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>; //===----------------------------------------------------------------------===// +// Program mask and addressing mode +//===----------------------------------------------------------------------===// + +// Insert Program Mask +def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>; + +// Set Program Mask +def : InstRW<[LSU, EndGroup], (instregex "SPM$")>; + +// Branch and link +def : InstRW<[FXU, FXU, LSU, Lat8, GroupAlone], (instregex "BAL(R)?$")>; + +// Test addressing mode +def : InstRW<[FXU, EndGroup], (instregex "TAM$")>; + +// Set addressing mode +def : InstRW<[LSU, EndGroup], (instregex "SAM(24|31|64)$")>; + +// Branch (and save) and set mode. +def : InstRW<[FXU, LSU, Lat4, GroupAlone], (instregex "BSM$")>; +def : InstRW<[FXU, FXU, LSU, Lat5, GroupAlone], (instregex "BASSM$")>; + +//===----------------------------------------------------------------------===// // Transactional execution //===----------------------------------------------------------------------===// @@ -541,9 +564,6 @@ def : InstRW<[FXU], (instregex "PPA$")>; // Miscellaneous Instructions. //===----------------------------------------------------------------------===// -// Insert Program Mask -def : InstRW<[FXU, Lat3, EndGroup], (instregex "IPM$")>; - // Find leftmost one def : InstRW<[FXU, Lat7, GroupAlone], (instregex "FLOGR$")>; diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt index 546e2f4..c8b49df 100644 --- a/llvm/test/MC/Disassembler/SystemZ/insns.txt +++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt @@ -778,6 +778,36 @@ # CHECK: ay %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x5a +# CHECK: bal %r0, 0 +0x45 0x00 0x00 0x00 + +# CHECK: bal %r1, 4095 +0x45 0x10 0x0f 0xff + +# CHECK: bal %r2, 0(%r1) +0x45 0x20 0x10 0x00 + +# CHECK: bal %r3, 0(%r15) +0x45 0x30 0xf0 0x00 + +# CHECK: bal %r14, 4095(%r1,%r15) +0x45 0xe1 0xff 0xff + +# CHECK: bal %r15, 4095(%r15,%r1) +0x45 0xff 0x1f 0xff + +# CHECK: balr %r0, %r1 +0x05 0x01 + +# CHECK: balr %r0, %r15 +0x05 0x0f + +# CHECK: balr %r14, %r9 +0x05 0xe9 + +# CHECK: balr %r15, %r1 +0x05 0xf1 + # CHECK: bas %r0, 0 0x4d 0x00 0x00 0x00 @@ -808,6 +838,30 @@ # CHECK: basr %r15, %r1 0x0d 0xf1 +# CHECK: bassm %r0, %r1 +0x0c 0x01 + +# CHECK: bassm %r0, %r15 +0x0c 0x0f + +# CHECK: bassm %r14, %r9 +0x0c 0xe9 + +# CHECK: bassm %r15, %r1 +0x0c 0xf1 + +# CHECK: bsm %r0, %r1 +0x0b 0x01 + +# CHECK: bsm %r0, %r15 +0x0b 0x0f + +# CHECK: bsm %r14, %r9 +0x0b 0xe9 + +# CHECK: bsm %r15, %r1 +0x0b 0xf1 + # CHECK: b 0 0x47 0xf0 0x00 0x00 @@ -7846,6 +7900,15 @@ # CHECK: sar %a15, %r15 0xb2 0x4e 0x00 0xff +# CHECK: sam24 +0x01 0x0c + +# CHECK: sam31 +0x01 0x0d + +# CHECK: sam64 +0x01 0x0e + # CHECK: sdbr %f0, %f0 0xb3 0x1b 0x00 0x00 @@ -8473,6 +8536,15 @@ # CHECK: sqdbr %f0, %f0 0xb3 0x15 0x00 0x00 +# CHECK: spm %r0 +0x04 0x00 + +# CHECK: spm %r1 +0x04 0x10 + +# CHECK: spm %r15 +0x04 0xf0 + # CHECK: sqdbr %f0, %f15 0xb3 0x15 0x00 0x0f @@ -9712,6 +9784,9 @@ # CHECK: sy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x5b +# CHECK: tam +0x01 0x0b + # CHECK: tabort 0 0xb2 0xfc 0x00 0x00 diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s index 81f6cfe..c5b1991 100644 --- a/llvm/test/MC/SystemZ/insn-bad.s +++ b/llvm/test/MC/SystemZ/insn-bad.s @@ -259,6 +259,14 @@ ay %r0, 524288 #CHECK: error: invalid operand +#CHECK: bal %r0, -1 +#CHECK: error: invalid operand +#CHECK: bal %r0, 4096 + + bal %r0, -1 + bal %r0, 4096 + +#CHECK: error: invalid operand #CHECK: bas %r0, -1 #CHECK: error: invalid operand #CHECK: bas %r0, 4096 diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s index da2decb..854cf1e 100644 --- a/llvm/test/MC/SystemZ/insn-good.s +++ b/llvm/test/MC/SystemZ/insn-good.s @@ -517,6 +517,30 @@ ay %r0, 524287(%r15,%r1) ay %r15, 0 +#CHECK: bal %r0, 0 # encoding: [0x45,0x00,0x00,0x00] +#CHECK: bal %r1, 4095 # encoding: [0x45,0x10,0x0f,0xff] +#CHECK: bal %r2, 0(%r1) # encoding: [0x45,0x20,0x10,0x00] +#CHECK: bal %r3, 0(%r15) # encoding: [0x45,0x30,0xf0,0x00] +#CHECK: bal %r14, 4095(%r1,%r15) # encoding: [0x45,0xe1,0xff,0xff] +#CHECK: bal %r15, 4095(%r15,%r1) # encoding: [0x45,0xff,0x1f,0xff] + + bal %r0, 0 + bal %r1, 4095 + bal %r2, 0(%r1) + bal %r3, 0(%r15) + bal %r14, 4095(%r1,%r15) + bal %r15, 4095(%r15,%r1) + +#CHECK: balr %r0, %r1 # encoding: [0x05,0x01] +#CHECK: balr %r0, %r15 # encoding: [0x05,0x0f] +#CHECK: balr %r14, %r9 # encoding: [0x05,0xe9] +#CHECK: balr %r15, %r1 # encoding: [0x05,0xf1] + + balr %r0,%r1 + balr %r0,%r15 + balr %r14,%r9 + balr %r15,%r1 + #CHECK: bas %r0, 0 # encoding: [0x4d,0x00,0x00,0x00] #CHECK: bas %r1, 4095 # encoding: [0x4d,0x10,0x0f,0xff] #CHECK: bas %r2, 0(%r1) # encoding: [0x4d,0x20,0x10,0x00] @@ -541,6 +565,26 @@ basr %r14,%r9 basr %r15,%r1 +#CHECK: bassm %r0, %r1 # encoding: [0x0c,0x01] +#CHECK: bassm %r0, %r15 # encoding: [0x0c,0x0f] +#CHECK: bassm %r14, %r9 # encoding: [0x0c,0xe9] +#CHECK: bassm %r15, %r1 # encoding: [0x0c,0xf1] + + bassm %r0,%r1 + bassm %r0,%r15 + bassm %r14,%r9 + bassm %r15,%r1 + +#CHECK: bsm %r0, %r1 # encoding: [0x0b,0x01] +#CHECK: bsm %r0, %r15 # encoding: [0x0b,0x0f] +#CHECK: bsm %r14, %r9 # encoding: [0x0b,0xe9] +#CHECK: bsm %r15, %r1 # encoding: [0x0b,0xf1] + + bsm %r0,%r1 + bsm %r0,%r15 + bsm %r14,%r9 + bsm %r15,%r1 + #CHECK: b 0 # encoding: [0x47,0xf0,0x00,0x00] #CHECK: b 4095 # encoding: [0x47,0xf0,0x0f,0xff] #CHECK: b 0(%r1) # encoding: [0x47,0xf0,0x10,0x00] @@ -8775,6 +8819,14 @@ sar %a7, %r8 sar %a15, %r15 +#CHECK: sam24 # encoding: [0x01,0x0c] +#CHECK: sam31 # encoding: [0x01,0x0d] +#CHECK: sam64 # encoding: [0x01,0x0e] + + sam24 + sam31 + sam64 + #CHECK: sdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1b] #CHECK: sdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1b] #CHECK: sdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1b] @@ -9183,6 +9235,14 @@ sly %r0, 524287(%r15,%r1) sly %r15, 0 +#CHECK: spm %r0 # encoding: [0x04,0x00] +#CHECK: spm %r1 # encoding: [0x04,0x10] +#CHECK: spm %r15 # encoding: [0x04,0xf0] + + spm %r0 + spm %r1 + spm %r15 + #CHECK: sqdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x15] #CHECK: sqdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x15] #CHECK: sqdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x15] @@ -10018,6 +10078,10 @@ sy %r0, 524287(%r15,%r1) sy %r15, 0 +#CHECK: tam # encoding: [0x01,0x0b] + + tam + #CHECK: tcdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x11] #CHECK: tcdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x11] #CHECK: tcdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x11] -- 2.7.4