From 3ff2022bb940237f10584d81da8d21bd62e76c7d Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Wed, 18 Apr 2018 20:34:23 +0000 Subject: [PATCH] [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293 --- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 5 +++-- llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 25 ++++++++++----------- llvm/test/CodeGen/RISCV/calling-conv.ll | 28 +++++++++--------------- llvm/test/CodeGen/RISCV/float-arith.ll | 2 -- llvm/test/CodeGen/RISCV/imm.ll | 2 -- llvm/test/CodeGen/RISCV/vararg.ll | 24 +++++++------------- 6 files changed, 32 insertions(+), 54 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 1c429da..00f0342 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -157,7 +157,8 @@ def simm21_lsb0 : Operand { def ixlenimm : Operand; // Standalone (codegen-only) immleaf patterns. -def simm32 : ImmLeaf(Imm);}]>; +def simm32 : ImmLeaf(Imm);}]>; +def simm32hi20 : ImmLeaf(Imm);}]>; // Addressing modes. // Necessary because a frameindex can't be matched directly in a pattern. @@ -521,7 +522,7 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ /// Immediates def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>; -// TODO: Add a pattern for immediates with all zeroes in the lower 12 bits. +def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>; def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>; /// Simple arithmetic operations diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll index 1fbc429..8ac6870 100644 --- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll @@ -15,10 +15,9 @@ declare i32 @llvm.ctpop.i32(i32) define i16 @test_bswap_i16(i16 %a) nounwind { ; RV32I-LABEL: test_bswap_i16: ; RV32I: # %bb.0: -; RV32I-NEXT: lui a1, 4080 -; RV32I-NEXT: mv a1, a1 -; RV32I-NEXT: slli a2, a0, 8 -; RV32I-NEXT: and a1, a2, a1 +; RV32I-NEXT: slli a1, a0, 8 +; RV32I-NEXT: lui a2, 4080 +; RV32I-NEXT: and a1, a1, a2 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: or a0, a0, a1 ; RV32I-NEXT: srli a0, a0, 16 @@ -36,10 +35,9 @@ define i32 @test_bswap_i32(i32 %a) nounwind { ; RV32I-NEXT: and a1, a2, a1 ; RV32I-NEXT: srli a2, a0, 24 ; RV32I-NEXT: or a1, a1, a2 -; RV32I-NEXT: lui a2, 4080 -; RV32I-NEXT: mv a2, a2 -; RV32I-NEXT: slli a3, a0, 8 -; RV32I-NEXT: and a2, a3, a2 +; RV32I-NEXT: slli a2, a0, 8 +; RV32I-NEXT: lui a3, 4080 +; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: or a0, a0, a2 ; RV32I-NEXT: or a0, a0, a1 @@ -57,19 +55,18 @@ define i64 @test_bswap_i64(i64 %a) nounwind { ; RV32I-NEXT: and a2, a2, a3 ; RV32I-NEXT: srli a4, a1, 24 ; RV32I-NEXT: or a2, a2, a4 -; RV32I-NEXT: lui a4, 4080 -; RV32I-NEXT: mv a4, a4 -; RV32I-NEXT: slli a5, a1, 8 -; RV32I-NEXT: and a5, a5, a4 +; RV32I-NEXT: slli a4, a1, 8 +; RV32I-NEXT: lui a5, 4080 +; RV32I-NEXT: and a4, a4, a5 ; RV32I-NEXT: slli a1, a1, 24 -; RV32I-NEXT: or a1, a1, a5 +; RV32I-NEXT: or a1, a1, a4 ; RV32I-NEXT: or a2, a1, a2 ; RV32I-NEXT: srli a1, a0, 8 ; RV32I-NEXT: and a1, a1, a3 ; RV32I-NEXT: srli a3, a0, 24 ; RV32I-NEXT: or a1, a1, a3 ; RV32I-NEXT: slli a3, a0, 8 -; RV32I-NEXT: and a3, a3, a4 +; RV32I-NEXT: and a3, a3, a5 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: or a0, a0, a3 ; RV32I-NEXT: or a1, a0, a1 diff --git a/llvm/test/CodeGen/RISCV/calling-conv.ll b/llvm/test/CodeGen/RISCV/calling-conv.ll index 8d752cb..31e9c93 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv.ll @@ -85,14 +85,13 @@ define i32 @caller_scalars() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 262464 -; RV32I-FPELIM-NEXT: mv a6, a0 ; RV32I-FPELIM-NEXT: lui a0, %hi(callee_scalars) ; RV32I-FPELIM-NEXT: addi a7, a0, %lo(callee_scalars) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a3, zero, 3 ; RV32I-FPELIM-NEXT: addi a4, zero, 4 +; RV32I-FPELIM-NEXT: lui a6, 262464 ; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: mv a5, zero ; RV32I-FPELIM-NEXT: jalr a7 @@ -106,14 +105,13 @@ define i32 @caller_scalars() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, 262464 -; RV32I-WITHFP-NEXT: mv a6, a0 ; RV32I-WITHFP-NEXT: lui a0, %hi(callee_scalars) ; RV32I-WITHFP-NEXT: addi a7, a0, %lo(callee_scalars) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a3, zero, 3 ; RV32I-WITHFP-NEXT: addi a4, zero, 4 +; RV32I-WITHFP-NEXT: lui a6, 262464 ; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: mv a5, zero ; RV32I-WITHFP-NEXT: jalr a7 @@ -187,6 +185,8 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -48 ; RV32I-FPELIM-NEXT: sw ra, 44(sp) +; RV32I-FPELIM-NEXT: lui a0, 524272 +; RV32I-FPELIM-NEXT: sw a0, 12(sp) ; RV32I-FPELIM-NEXT: sw zero, 8(sp) ; RV32I-FPELIM-NEXT: sw zero, 4(sp) ; RV32I-FPELIM-NEXT: sw zero, 0(sp) @@ -195,9 +195,6 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-FPELIM-NEXT: sw zero, 28(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: sw a0, 24(sp) -; RV32I-FPELIM-NEXT: lui a0, 524272 -; RV32I-FPELIM-NEXT: mv a0, a0 -; RV32I-FPELIM-NEXT: sw a0, 12(sp) ; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars) ; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_large_scalars) ; RV32I-FPELIM-NEXT: addi a0, sp, 24 @@ -213,6 +210,8 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 44(sp) ; RV32I-WITHFP-NEXT: sw s0, 40(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 48 +; RV32I-WITHFP-NEXT: lui a0, 524272 +; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: sw zero, -40(s0) ; RV32I-WITHFP-NEXT: sw zero, -44(s0) ; RV32I-WITHFP-NEXT: sw zero, -48(s0) @@ -221,9 +220,6 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: sw a0, -24(s0) -; RV32I-WITHFP-NEXT: lui a0, 524272 -; RV32I-WITHFP-NEXT: mv a0, a0 -; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars) ; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_large_scalars) ; RV32I-WITHFP-NEXT: addi a0, s0, -24 @@ -306,6 +302,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-FPELIM-NEXT: sw a0, 4(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 9 ; RV32I-FPELIM-NEXT: sw a0, 0(sp) +; RV32I-FPELIM-NEXT: lui a0, 524272 +; RV32I-FPELIM-NEXT: sw a0, 28(sp) ; RV32I-FPELIM-NEXT: sw zero, 24(sp) ; RV32I-FPELIM-NEXT: sw zero, 20(sp) ; RV32I-FPELIM-NEXT: sw zero, 16(sp) @@ -314,9 +312,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-FPELIM-NEXT: sw zero, 44(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 8 ; RV32I-FPELIM-NEXT: sw a0, 40(sp) -; RV32I-FPELIM-NEXT: lui a0, 524272 -; RV32I-FPELIM-NEXT: mv a0, a0 -; RV32I-FPELIM-NEXT: sw a0, 28(sp) ; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs) ; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 @@ -342,6 +337,8 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-WITHFP-NEXT: sw a0, 4(sp) ; RV32I-WITHFP-NEXT: addi a0, zero, 9 ; RV32I-WITHFP-NEXT: sw a0, 0(sp) +; RV32I-WITHFP-NEXT: lui a0, 524272 +; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: sw zero, -40(s0) ; RV32I-WITHFP-NEXT: sw zero, -44(s0) ; RV32I-WITHFP-NEXT: sw zero, -48(s0) @@ -350,9 +347,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: addi a0, zero, 8 ; RV32I-WITHFP-NEXT: sw a0, -24(s0) -; RV32I-WITHFP-NEXT: lui a0, 524272 -; RV32I-WITHFP-NEXT: mv a0, a0 -; RV32I-WITHFP-NEXT: sw a0, -36(s0) ; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs) ; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 @@ -987,7 +981,6 @@ define fp128 @callee_large_scalar_ret() nounwind { ; RV32I-FPELIM-LABEL: callee_large_scalar_ret: ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: lui a1, 524272 -; RV32I-FPELIM-NEXT: mv a1, a1 ; RV32I-FPELIM-NEXT: sw a1, 12(a0) ; RV32I-FPELIM-NEXT: sw zero, 8(a0) ; RV32I-FPELIM-NEXT: sw zero, 4(a0) @@ -1001,7 +994,6 @@ define fp128 @callee_large_scalar_ret() nounwind { ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 ; RV32I-WITHFP-NEXT: lui a1, 524272 -; RV32I-WITHFP-NEXT: mv a1, a1 ; RV32I-WITHFP-NEXT: sw a1, 12(a0) ; RV32I-WITHFP-NEXT: sw zero, 8(a0) ; RV32I-WITHFP-NEXT: sw zero, 4(a0) diff --git a/llvm/test/CodeGen/RISCV/float-arith.ll b/llvm/test/CodeGen/RISCV/float-arith.ll index c7c5f91..f3ec61b 100644 --- a/llvm/test/CodeGen/RISCV/float-arith.ll +++ b/llvm/test/CodeGen/RISCV/float-arith.ll @@ -84,7 +84,6 @@ define float @fneg_s(float %a) nounwind { ; RV32IF-LABEL: fneg_s: ; RV32IF: # %bb.0: ; RV32IF-NEXT: lui a1, 524288 -; RV32IF-NEXT: mv a1, a1 ; RV32IF-NEXT: xor a0, a0, a1 ; RV32IF-NEXT: ret %1 = fsub float -0.0, %a @@ -97,7 +96,6 @@ define float @fsgnjn_s(float %a, float %b) nounwind { ; RV32IF-LABEL: fsgnjn_s: ; RV32IF: # %bb.0: ; RV32IF-NEXT: lui a2, 524288 -; RV32IF-NEXT: mv a2, a2 ; RV32IF-NEXT: xor a1, a1, a2 ; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft1, a0 diff --git a/llvm/test/CodeGen/RISCV/imm.ll b/llvm/test/CodeGen/RISCV/imm.ll index ae10424..b9e2f8a 100644 --- a/llvm/test/CodeGen/RISCV/imm.ll +++ b/llvm/test/CodeGen/RISCV/imm.ll @@ -50,7 +50,6 @@ define i32 @pos_i32_hi20_only() nounwind { ; RV32I-LABEL: pos_i32_hi20_only: ; RV32I: # %bb.0: ; RV32I-NEXT: lui a0, 16 -; RV32I-NEXT: mv a0, a0 ; RV32I-NEXT: ret ret i32 65536 } @@ -59,7 +58,6 @@ define i32 @neg_i32_hi20_only() nounwind { ; RV32I-LABEL: neg_i32_hi20_only: ; RV32I: # %bb.0: ; RV32I-NEXT: lui a0, 1048560 -; RV32I-NEXT: mv a0, a0 ; RV32I-NEXT: ret ret i32 -65536 } diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll index 61a6178..c930f7d 100644 --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -264,10 +264,9 @@ define void @va1_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 261888 -; RV32I-FPELIM-NEXT: mv a3, a0 ; RV32I-FPELIM-NEXT: lui a0, %hi(va1) ; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1) +; RV32I-FPELIM-NEXT: lui a3, 261888 ; RV32I-FPELIM-NEXT: addi a4, zero, 2 ; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: jalr a0 @@ -281,10 +280,9 @@ define void @va1_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, 261888 -; RV32I-WITHFP-NEXT: mv a3, a0 ; RV32I-WITHFP-NEXT: lui a0, %hi(va1) ; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1) +; RV32I-WITHFP-NEXT: lui a3, 261888 ; RV32I-WITHFP-NEXT: addi a4, zero, 2 ; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: jalr a0 @@ -472,10 +470,9 @@ define void @va2_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 261888 -; RV32I-FPELIM-NEXT: mv a3, a0 ; RV32I-FPELIM-NEXT: lui a0, %hi(va2) ; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2) +; RV32I-FPELIM-NEXT: lui a3, 261888 ; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: jalr a0 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) @@ -488,10 +485,9 @@ define void @va2_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, 261888 -; RV32I-WITHFP-NEXT: mv a3, a0 ; RV32I-WITHFP-NEXT: lui a0, %hi(va2) ; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2) +; RV32I-WITHFP-NEXT: lui a3, 261888 ; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: jalr a0 ; RV32I-WITHFP-NEXT: lw s0, 8(sp) @@ -716,13 +712,11 @@ define void @va3_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, 261888 -; RV32I-FPELIM-NEXT: mv a2, a0 -; RV32I-FPELIM-NEXT: lui a0, 262144 -; RV32I-FPELIM-NEXT: mv a5, a0 ; RV32I-FPELIM-NEXT: lui a0, %hi(va3) ; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3) ; RV32I-FPELIM-NEXT: addi a0, zero, 2 +; RV32I-FPELIM-NEXT: lui a2, 261888 +; RV32I-FPELIM-NEXT: lui a5, 262144 ; RV32I-FPELIM-NEXT: mv a1, zero ; RV32I-FPELIM-NEXT: mv a4, zero ; RV32I-FPELIM-NEXT: jalr a3 @@ -736,13 +730,11 @@ define void @va3_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, 261888 -; RV32I-WITHFP-NEXT: mv a2, a0 -; RV32I-WITHFP-NEXT: lui a0, 262144 -; RV32I-WITHFP-NEXT: mv a5, a0 ; RV32I-WITHFP-NEXT: lui a0, %hi(va3) ; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3) ; RV32I-WITHFP-NEXT: addi a0, zero, 2 +; RV32I-WITHFP-NEXT: lui a2, 261888 +; RV32I-WITHFP-NEXT: lui a5, 262144 ; RV32I-WITHFP-NEXT: mv a1, zero ; RV32I-WITHFP-NEXT: mv a4, zero ; RV32I-WITHFP-NEXT: jalr a3 -- 2.7.4