From 3fe71809a5d666385575358b579aae2b8a96dd07 Mon Sep 17 00:00:00 2001 From: Yashwant Singh Date: Fri, 23 Sep 2022 11:11:39 +0530 Subject: [PATCH] Introduce predicate for a atomic operations in GMIR Reviewed By: arsenm, sameerds Differential Revision: https://reviews.llvm.org/D134266 --- llvm/include/llvm/CodeGen/TargetInstrInfo.h | 5 +++++ llvm/include/llvm/Support/TargetOpcodes.def | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h index 65fba77..02eaf93 100644 --- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h +++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h @@ -110,6 +110,11 @@ public: return Opc <= TargetOpcode::GENERIC_OP_END; } + static bool isGenericAtomicRMWOpcode(unsigned Opc) { + return Opc >= TargetOpcode::GENERIC_ATOMICRMW_OP_START && + Opc <= TargetOpcode::GENERIC_ATOMICRMW_OP_END; + } + /// Given a machine instruction descriptor, returns the register /// class constraint for OpNum, or NULL. virtual diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def index 5d6be0f..52da565 100644 --- a/llvm/include/llvm/Support/TargetOpcodes.def +++ b/llvm/include/llvm/Support/TargetOpcodes.def @@ -387,6 +387,12 @@ HANDLE_TARGET_OPCODE(G_ATOMICRMW_FSUB) HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMAX) HANDLE_TARGET_OPCODE(G_ATOMICRMW_FMIN) +// Marker for start of Generic AtomicRMW opcodes +HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_START, G_ATOMICRMW_XCHG) + +// Marker for end of Generic AtomicRMW opcodes +HANDLE_TARGET_OPCODE_MARKER(GENERIC_ATOMICRMW_OP_END, G_ATOMICRMW_FMIN) + // Generic atomic fence HANDLE_TARGET_OPCODE(G_FENCE) -- 2.7.4