From 3fd229a447cd28a70bfd921f617bc6c3553b8fdd Mon Sep 17 00:00:00 2001 From: Sudakshina Das Date: Wed, 26 Sep 2018 10:54:07 +0100 Subject: [PATCH] [PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys) This patch adds the DC CVADP instruction. Since this has a separate identification mechanism a new feature bit is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. --- gas/ChangeLog | 6 ++++++ gas/testsuite/gas/aarch64/illegal-sysreg-4.l | 1 + gas/testsuite/gas/aarch64/sysreg-4.d | 1 + gas/testsuite/gas/aarch64/sysreg-4.s | 1 + include/ChangeLog | 4 ++++ include/opcode/aarch64.h | 5 ++++- opcodes/ChangeLog | 5 +++++ opcodes/aarch64-opc.c | 6 ++++++ 8 files changed, 28 insertions(+), 1 deletion(-) diff --git a/gas/ChangeLog b/gas/ChangeLog index 6fa3e72..f958277 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,11 @@ 2018-10-09 Sudakshina Das + * testsuite/gas/aarch64/sysreg-4.s: Test instruction. + * testsuite/gas/aarch64/sysreg-4.d: Likewise. + * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise. + +2018-10-09 Sudakshina Das + * config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New. (parse_operands): Add entry for AARCH64_OPND_SYSREG_SR. (md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh diff --git a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l index 68471a1..f3167e3 100644 --- a/gas/testsuite/gas/aarch64/illegal-sysreg-4.l +++ b/gas/testsuite/gas/aarch64/illegal-sysreg-4.l @@ -5,3 +5,4 @@ [^:]*:[0-9]+: Error: selected processor does not support `dvp rctx,x2' [^:]*:[0-9]+: Error: selected processor does not support system register name 'rctx' [^:]*:[0-9]+: Error: selected processor does not support `cpp rctx,x3' +[^:]*:[0-9]+: Error: selected processor does not support system register name 'cvadp' diff --git a/gas/testsuite/gas/aarch64/sysreg-4.d b/gas/testsuite/gas/aarch64/sysreg-4.d index f3ea5d1..1c14016 100644 --- a/gas/testsuite/gas/aarch64/sysreg-4.d +++ b/gas/testsuite/gas/aarch64/sysreg-4.d @@ -10,3 +10,4 @@ Disassembly of section \.text: .*: d50b7381 cfp rctx, x1 .*: d50b73a2 dvp rctx, x2 .*: d50b73e3 cpp rctx, x3 +.*: d50b7d24 dc cvadp, x4 diff --git a/gas/testsuite/gas/aarch64/sysreg-4.s b/gas/testsuite/gas/aarch64/sysreg-4.s index 6ec069a..49907c0 100644 --- a/gas/testsuite/gas/aarch64/sysreg-4.s +++ b/gas/testsuite/gas/aarch64/sysreg-4.s @@ -3,3 +3,4 @@ func: cfp rctx, x1 dvp rctx, x2 cpp rctx, x3 + dc cvadp, x4 diff --git a/include/ChangeLog b/include/ChangeLog index be7072a..499312d 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,9 @@ 2018-10-09 Sudakshina Das + * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. + +2018-10-09 Sudakshina Das + * opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New. (AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default. (aarch64_opnd): Add AARCH64_OPND_SYSREG_SR. diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 7b542c9..7656a57 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -72,6 +72,8 @@ typedef uint32_t aarch64_insn; #define AARCH64_FEATURE_SB 0x10000000000ULL /* Execution and Data Prediction Restriction instructions. */ #define AARCH64_FEATURE_PREDRES 0x20000000000ULL +/* DC CVADP. */ +#define AARCH64_FEATURE_CVADP 0x40000000000ULL /* Architectures are the sum of the base and extensions. */ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ @@ -100,7 +102,8 @@ typedef uint32_t aarch64_insn; | AARCH64_FEATURE_FLAGMANIP \ | AARCH64_FEATURE_FRINTTS \ | AARCH64_FEATURE_SB \ - | AARCH64_FEATURE_PREDRES) + | AARCH64_FEATURE_PREDRES \ + | AARCH64_FEATURE_CVADP) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 8a5cbf5..37bfeeb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,10 @@ 2018-10-09 Sudakshina Das + * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. + (aarch64_sys_ins_reg_supported_p): New check for above. + +2018-10-09 Sudakshina Das + * aarch64-dis.c (aarch64_ext_sysins_op): Add case for AARCH64_OPND_SYSREG_SR. * aarch64-opc.c (aarch64_print_operand): Likewise. diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index f3c436c..9562ba8 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4349,6 +4349,7 @@ const aarch64_sys_ins_reg aarch64_sys_regs_dc[] = { "csw", CPENS (0, C7, C10, 2), F_HASXT }, { "cvau", CPENS (3, C7, C11, 1), F_HASXT }, { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT }, + { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT }, { "civac", CPENS (3, C7, C14, 1), F_HASXT }, { "cisw", CPENS (0, C7, C14, 2), F_HASXT }, { 0, CPENS(0,0,0,0), 0 } @@ -4488,6 +4489,11 @@ aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2)) return FALSE; + /* DC CVADP. Values are from aarch64_sys_regs_dc. */ + if (reg->value == CPENS (3, C7, C13, 1) + && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP)) + return FALSE; + /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */ if ((reg->value == CPENS (0, C7, C9, 0) || reg->value == CPENS (0, C7, C9, 1)) -- 2.7.4