From 3f7068ad986d7f44f47faec78597a5e62b07b20b Mon Sep 17 00:00:00 2001 From: Sam Elliott Date: Mon, 17 Aug 2020 13:10:27 +0100 Subject: [PATCH] [RISCV] Enable the use of the old mucounteren name The RISC-V Privileged Specification 1.11 defines `mcountinhibit`, which has the same numeric CSR value as `mucounteren` from 1.09.1. This patch enables the use of the old `mucounteren` name. Patch by Yuichi Sugiyama. Reviewed By: lenary, jrtc27, pzheng Differential Revision: https://reviews.llvm.org/D85067 --- llvm/lib/Target/RISCV/RISCVSystemOperands.td | 2 ++ llvm/test/MC/RISCV/machine-csr-names.s | 14 ++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td index 8e75647..16399fe 100644 --- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td +++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td @@ -310,7 +310,9 @@ def: SysReg<"mhpmcounter31h", 0xB9F>; //===-------------------------- // Machine Counter Setup //===-------------------------- +let AltName = "mucounteren" in // Privileged spec v1.9.1 Name def : SysReg<"mcountinhibit", 0x320>; + def : SysReg<"mhpmevent3", 0x323>; def : SysReg<"mhpmevent4", 0x324>; def : SysReg<"mhpmevent5", 0x325>; diff --git a/llvm/test/MC/RISCV/machine-csr-names.s b/llvm/test/MC/RISCV/machine-csr-names.s index 93ecd7e..dbc4f5f 100644 --- a/llvm/test/MC/RISCV/machine-csr-names.s +++ b/llvm/test/MC/RISCV/machine-csr-names.s @@ -863,6 +863,20 @@ csrrs t1, mcountinhibit, zero # uimm12 csrrs t2, 0x320, zero +# mucounteren +# name +# CHECK-INST: csrrs t1, mcountinhibit, zero +# CHECK-ENC: encoding: [0x73,0x23,0x00,0x32] +# CHECK-INST-ALIAS: csrr t1, mcountinhibit +# uimm12 +# CHECK-INST: csrrs t2, mcountinhibit, zero +# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x32] +# CHECK-INST-ALIAS: csrr t2, mcountinhibit +# name +csrrs t1, mucounteren, zero +# uimm12 +csrrs t2, 0x320, zero + # mhpmevent3 # name # CHECK-INST: csrrs t1, mhpmevent3, zero -- 2.7.4