From 3f703b071e43d5337625f796d700a397156e08e4 Mon Sep 17 00:00:00 2001 From: wangpc Date: Wed, 18 Jan 2023 14:24:23 +0800 Subject: [PATCH] [RISCV][NFC] Move compressInst/uncompressInst to RISCVBaseInfo We have several usages of compressInst/uncompressInst in different files, which results in duplicated code. We move their implementations to RISCVBaseInfo under namespace RISCVRVC to remove these duplications. Reviewed By: craig.topper, asb Differential Revision: https://reviews.llvm.org/D141897 --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 6 +----- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp | 17 +++++++++++++++++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 5 +++++ llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 6 +----- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp | 4 +--- 5 files changed, 25 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index c1549ef..9752e39 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -45,10 +45,6 @@ using namespace llvm; #define DEBUG_TYPE "riscv-asm-parser" -// Include the auto-generated portion of the compress emitter. -#define GEN_COMPRESS_INSTR -#include "RISCVGenCompressInstEmitter.inc" - STATISTIC(RISCVNumInstrsCompressed, "Number of RISC-V Compressed instructions emitted"); @@ -2316,7 +2312,7 @@ bool RISCVAsmParser::parseDirectiveVariantCC() { void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) { MCInst CInst; - bool Res = compressInst(CInst, Inst, getSTI()); + bool Res = RISCVRVC::compress(CInst, Inst, getSTI()); if (Res) ++RISCVNumInstrsCompressed; S.emitInstruction((Res ? CInst : Inst), getSTI()); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp index 70fe3b9..3292df6 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -14,6 +14,8 @@ #include "RISCVBaseInfo.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/Triple.h" +#include "llvm/MC/MCInst.h" +#include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" #include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/TargetParser.h" @@ -197,4 +199,19 @@ unsigned RISCVVType::getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul) { return (SEW * 8) / LMul; } +// Include the auto-generated portion of the compress emitter. +#define GEN_UNCOMPRESS_INSTR +#define GEN_COMPRESS_INSTR +#include "RISCVGenCompressInstEmitter.inc" + +bool RISCVRVC::compress(MCInst &OutInst, const MCInst &MI, + const MCSubtargetInfo &STI) { + return compressInst(OutInst, MI, STI); +} + +bool RISCVRVC::uncompress(MCInst &OutInst, const MCInst &MI, + const MCSubtargetInfo &STI) { + return uncompressInst(OutInst, MI, STI); +} + } // namespace llvm diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index 06836e9..2cf2045 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -467,6 +467,11 @@ unsigned getSEWLMULRatio(unsigned SEW, RISCVII::VLMUL VLMul); } // namespace RISCVVType +namespace RISCVRVC { +bool compress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI); +bool uncompress(MCInst &OutInst, const MCInst &MI, const MCSubtargetInfo &STI); +} // namespace RISCVRVC + } // namespace llvm #endif diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 5d2d141..a4fbba7 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -30,10 +30,6 @@ using namespace llvm; #define PRINT_ALIAS_INSTR #include "RISCVGenAsmWriter.inc" -// Include the auto-generated portion of the compress emitter. -#define GEN_UNCOMPRESS_INSTR -#include "RISCVGenCompressInstEmitter.inc" - static cl::opt NoAliases("riscv-no-aliases", cl::desc("Disable the emission of assembler pseudo instructions"), @@ -70,7 +66,7 @@ void RISCVInstPrinter::printInst(const MCInst *MI, uint64_t Address, const MCInst *NewMI = MI; MCInst UncompressedMI; if (PrintAliases && !NoAliases) - Res = uncompressInst(UncompressedMI, *MI, STI); + Res = RISCVRVC::uncompress(UncompressedMI, *MI, STI); if (Res) NewMI = const_cast(&UncompressedMI); if (!PrintAliases || NoAliases || !printAliasInstr(NewMI, Address, STI, O)) diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index f6b9e9e..c315758 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -89,11 +89,9 @@ private: }; } -#define GEN_COMPRESS_INSTR -#include "RISCVGenCompressInstEmitter.inc" void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) { MCInst CInst; - bool Res = compressInst(CInst, Inst, *STI); + bool Res = RISCVRVC::compress(CInst, Inst, *STI); if (Res) ++RISCVNumInstrsCompressed; AsmPrinter::EmitToStreamer(*OutStreamer, Res ? CInst : Inst); -- 2.7.4