From 3f34bd5f3f5c5b86df0e98328c60fd1626387889 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Sat, 15 Jul 2023 14:05:55 -0400 Subject: [PATCH] radeonsi: cosmetic changes to radeon_opt_* macros Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/gallium/drivers/radeonsi/si_build_pm4.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_build_pm4.h b/src/gallium/drivers/radeonsi/si_build_pm4.h index 03c5edb..425d19c 100644 --- a/src/gallium/drivers/radeonsi/si_build_pm4.h +++ b/src/gallium/drivers/radeonsi/si_build_pm4.h @@ -143,11 +143,12 @@ #define radeon_opt_push_gfx_sh_reg(offset, reg, val) do { \ unsigned __value = val; \ - if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \ - sctx->tracked_regs.other_reg_value[reg] != __value) { \ + unsigned __reg = reg; \ + if (((sctx->tracked_regs.other_reg_saved_mask >> (__reg)) & 0x1) != 0x1 || \ + sctx->tracked_regs.other_reg_value[__reg] != __value) { \ radeon_push_gfx_sh_reg(offset, __value); \ - sctx->tracked_regs.other_reg_saved_mask |= BITFIELD64_BIT(reg); \ - sctx->tracked_regs.other_reg_value[reg] = __value; \ + sctx->tracked_regs.other_reg_saved_mask |= BITFIELD_BIT(__reg); \ + sctx->tracked_regs.other_reg_value[__reg] = __value; \ } \ } while (0) @@ -156,7 +157,7 @@ if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \ sctx->tracked_regs.other_reg_value[reg] != __value) { \ radeon_push_compute_sh_reg(offset, __value); \ - sctx->tracked_regs.other_reg_saved_mask |= BITFIELD64_BIT(reg); \ + sctx->tracked_regs.other_reg_saved_mask |= BITFIELD_BIT(reg); \ sctx->tracked_regs.other_reg_value[reg] = __value; \ } \ } while (0) @@ -315,7 +316,7 @@ if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \ sctx->tracked_regs.other_reg_value[reg] != __value) { \ radeon_set_sh_reg(offset, __value); \ - sctx->tracked_regs.other_reg_saved_mask |= BITFIELD64_BIT(reg); \ + sctx->tracked_regs.other_reg_saved_mask |= BITFIELD_BIT(reg); \ sctx->tracked_regs.other_reg_value[reg] = __value; \ } \ } while (0) @@ -362,7 +363,7 @@ if (((sctx->tracked_regs.other_reg_saved_mask >> (reg)) & 0x1) != 0x1 || \ sctx->tracked_regs.other_reg_value[reg] != __value) { \ radeon_set_sh_reg_idx3(sctx, offset, __value); \ - sctx->tracked_regs.other_reg_saved_mask |= BITFIELD64_BIT(reg); \ + sctx->tracked_regs.other_reg_saved_mask |= BITFIELD_BIT(reg); \ sctx->tracked_regs.other_reg_value[reg] = __value; \ } \ } while (0) @@ -417,7 +418,7 @@ si_get_user_data_base(enum amd_gfx_level gfx_level, enum si_has_tess has_tess, { switch (shader) { case PIPE_SHADER_VERTEX: - /* VS can be bound as VS, ES, or LS. */ + /* VS can be bound as VS, ES, LS, or GS. */ if (has_tess) { if (gfx_level >= GFX10) { return R_00B430_SPI_SHADER_USER_DATA_HS_0; -- 2.7.4