From 3f30f2d1dbb3228b8468b26239fe60c2974ce2ac Mon Sep 17 00:00:00 2001 From: Bill Schmidt Date: Wed, 2 Feb 2022 21:24:22 -0600 Subject: [PATCH] rs6000: Fix LE code gen for vec_cnt[lt]z_lsbb [PR95082] These built-ins were misimplemented as always having big-endian semantics. 2022-01-18 Bill Schmidt gcc/ PR target/95082 * config/rs6000/rs6000-builtin.cc (rs6000_expand_builtin): Handle endianness for vclzlsbb and vctzlsbb. * config/rs6000/rs6000-builtins.def (VCLZLSBB_V16QI): Change default pattern and indicate a different pattern will be used for big endian. (VCLZLSBB_V4SI): Likewise. (VCLZLSBB_V8HI): Likewise. (VCTZLSBB_V16QI): Likewise. (VCTZLSBB_V4SI): Likewise. (VCTZLSBB_V8HI): Likewise. gcc/testsuite/ PR target/95082 * gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c: Restrict to -mbig. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c: New. * gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c: New. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c: Restrict to -mbig. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c: Likewise. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c: New. * gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c: New. --- gcc/config/rs6000/rs6000-builtin.cc | 12 ++++++++++++ gcc/config/rs6000/rs6000-builtins.def | 12 ++++++------ gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c | 2 +- gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c | 15 +++++++++++++++ 10 files changed, 82 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c diff --git a/gcc/config/rs6000/rs6000-builtin.cc b/gcc/config/rs6000/rs6000-builtin.cc index 005f936..69f8cee 100644 --- a/gcc/config/rs6000/rs6000-builtin.cc +++ b/gcc/config/rs6000/rs6000-builtin.cc @@ -3485,6 +3485,18 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, icode = CODE_FOR_vsx_store_v8hi; else if (fcode == RS6000_BIF_ST_ELEMREV_V16QI) icode = CODE_FOR_vsx_store_v16qi; + else if (fcode == RS6000_BIF_VCLZLSBB_V16QI) + icode = CODE_FOR_vclzlsbb_v16qi; + else if (fcode == RS6000_BIF_VCLZLSBB_V4SI) + icode = CODE_FOR_vclzlsbb_v4si; + else if (fcode == RS6000_BIF_VCLZLSBB_V8HI) + icode = CODE_FOR_vclzlsbb_v8hi; + else if (fcode == RS6000_BIF_VCTZLSBB_V16QI) + icode = CODE_FOR_vctzlsbb_v16qi; + else if (fcode == RS6000_BIF_VCTZLSBB_V4SI) + icode = CODE_FOR_vctzlsbb_v4si; + else if (fcode == RS6000_BIF_VCTZLSBB_V8HI) + icode = CODE_FOR_vctzlsbb_v8hi; else gcc_unreachable (); } diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index a8ebb4a..7f527b6 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -2550,13 +2550,13 @@ VBPERMD altivec_vbpermd {} const signed int __builtin_altivec_vclzlsbb_v16qi (vsc); - VCLZLSBB_V16QI vclzlsbb_v16qi {} + VCLZLSBB_V16QI vctzlsbb_v16qi {endian} const signed int __builtin_altivec_vclzlsbb_v4si (vsi); - VCLZLSBB_V4SI vclzlsbb_v4si {} + VCLZLSBB_V4SI vctzlsbb_v4si {endian} const signed int __builtin_altivec_vclzlsbb_v8hi (vss); - VCLZLSBB_V8HI vclzlsbb_v8hi {} + VCLZLSBB_V8HI vctzlsbb_v8hi {endian} const vsc __builtin_altivec_vctzb (vsc); VCTZB ctzv16qi2 {} @@ -2571,13 +2571,13 @@ VCTZW ctzv4si2 {} const signed int __builtin_altivec_vctzlsbb_v16qi (vsc); - VCTZLSBB_V16QI vctzlsbb_v16qi {} + VCTZLSBB_V16QI vclzlsbb_v16qi {endian} const signed int __builtin_altivec_vctzlsbb_v4si (vsi); - VCTZLSBB_V4SI vctzlsbb_v4si {} + VCTZLSBB_V4SI vclzlsbb_v4si {endian} const signed int __builtin_altivec_vctzlsbb_v8hi (vss); - VCTZLSBB_V8HI vctzlsbb_v8hi {} + VCTZLSBB_V8HI vclzlsbb_v8hi {endian} const signed int __builtin_altivec_vcmpaeb_p (vsc, vsc); VCMPAEB_P vector_ae_v16qi_p {} diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c index 0faf233..dc92d6f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c index 201ed17..6fefb89 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c new file mode 100644 index 0000000..6ee31a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_leading_zero_byte_bits (vector signed char *arg1_p) +{ + vector signed char arg_1 = *arg1_p; + + return vec_cntlz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vctzlsbb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c new file mode 100644 index 0000000..6105091 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cntlz-lsbb-4.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_leading_zero_byte_bits (vector unsigned char *arg1_p) +{ + vector unsigned char arg_1 = *arg1_p; + + return vec_cntlz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vctzlsbb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c index 70a398a..68d6c5f 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-0.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c index f6d41e3..f971ea0 100644 --- a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-1.c @@ -1,6 +1,6 @@ /* { dg-do compile { target { powerpc*-*-* } } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mdejagnu-cpu=power9" } */ +/* { dg-options "-mdejagnu-cpu=power9 -mbig" } */ #include diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c new file mode 100644 index 0000000..a9245d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-3.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_trailing_zero_byte_bits (vector signed char *arg1_p) +{ + vector signed char arg_1 = *arg1_p; + + return vec_cnttz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vclzlsbb" } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c new file mode 100644 index 0000000..71fea53 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsu/vec-cnttz-lsbb-4.c @@ -0,0 +1,15 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -mlittle" } */ + +#include + +int +count_trailing_zero_byte_bits (vector unsigned char *arg1_p) +{ + vector unsigned char arg_1 = *arg1_p; + + return vec_cnttz_lsbb (arg_1); +} + +/* { dg-final { scan-assembler "vclzlsbb" } } */ -- 2.7.4