From 3f2dbec652f8406a314b76bbb5e715a03393db76 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Thu, 29 Mar 2018 21:03:53 +0000 Subject: [PATCH] [X86] Remove ReadAfterLd from BMI and TBM instructions that don't have a register operand in their memory form The memory form of these instructions only read an input from memory. They don't have any register operands. Differential Revision: https://reviews.llvm.org/D44836 llvm-svn: 328828 --- llvm/lib/Target/X86/X86InstrInfo.td | 6 +++--- llvm/lib/Target/X86/X86ScheduleZnver1.td | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/X86/X86InstrInfo.td b/llvm/lib/Target/X86/X86InstrInfo.td index 1dd464c..b246c8c 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.td +++ b/llvm/lib/Target/X86/X86InstrInfo.td @@ -2341,7 +2341,7 @@ let hasSideEffects = 0 in { let mayLoad = 1 in def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), - [], IIC_UNARY_MEM>, T8PS, VEX_4V, Sched<[WriteALULd, ReadAfterLd]>; + [], IIC_UNARY_MEM>, T8PS, VEX_4V, Sched<[WriteALULd]>; } } @@ -2540,7 +2540,7 @@ multiclass tbm_ternary_imm_intr opc, RegisterClass RC, string OpcodeStr, !strconcat(OpcodeStr, "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), [(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))], - IIC_BIN_MEM>, XOP, XOPA, Sched<[WriteALULd, ReadAfterLd]>; + IIC_BIN_MEM>, XOP, XOPA, Sched<[WriteALULd]>; } defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr{l}", i32mem, loadi32, @@ -2560,7 +2560,7 @@ let hasSideEffects = 0 in { let mayLoad = 1 in def rm : I, XOP_4V, XOP9, Sched<[WriteALULd, ReadAfterLd]>; + [], IIC_BIN_MEM>, XOP_4V, XOP9, Sched<[WriteALULd]>; } } diff --git a/llvm/lib/Target/X86/X86ScheduleZnver1.td b/llvm/lib/Target/X86/X86ScheduleZnver1.td index 33472c8..74f32bc 100644 --- a/llvm/lib/Target/X86/X86ScheduleZnver1.td +++ b/llvm/lib/Target/X86/X86ScheduleZnver1.td @@ -566,7 +566,7 @@ def : InstRW<[ZnWriteBTRSCm], (instregex "BT(R|S|C)(16|32|64)m(r|i8)")>; // r,r. def : InstRW<[ZnWriteALULat2], (instregex "BLS(I|MSK|R)(32|64)rr")>; // r,m. -def : InstRW<[ZnWriteALULat2Ld, ReadAfterLd], (instregex "BLS(I|MSK|R)(32|64)rm")>; +def : InstRW<[ZnWriteALULat2Ld], (instregex "BLS(I|MSK|R)(32|64)rm")>; // CLD STD. def : InstRW<[WriteALU], (instregex "STD", "CLD")>; -- 2.7.4