From 3e678cb77264907fbc2899c291ce23af308073ff Mon Sep 17 00:00:00 2001 From: Fraser Cormack Date: Tue, 19 Apr 2022 09:25:40 +0100 Subject: [PATCH] [RISCV] Don't emit fractional VIDs with negative steps We can't shift-right negative numbers to divide them, so avoid emitting such sequences. Use negative numerators as a proxy for this situation, since the indices are always non-negative. An alternative strategy could be to add a compiler flag to emit division instructions, which would at least allow us to test the VID sequence matching itself. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D123796 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ++- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll | 14 +++++++------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 2d64acd..6e19b83 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -2186,7 +2186,8 @@ static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG, // a single addi instruction. if (((StepOpcode == ISD::MUL && isInt<12>(SplatStepVal)) || (StepOpcode == ISD::SHL && isUInt<5>(SplatStepVal))) && - isPowerOf2_32(StepDenominator) && isInt<5>(Addend)) { + isPowerOf2_32(StepDenominator) && + (SplatStepVal >= 0 || StepDenominator == 1) && isInt<5>(Addend)) { SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, ContainerVT, Mask, VL); // Convert right out of the scalable type so we can use standard ISD // nodes for the rest of the computation. If we used scalable types with diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll index 925ea68..8c9d056 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll @@ -746,17 +746,17 @@ define <4 x i8> @buildvec_not_vid_v4i8_2() { ret <4 x i8> } -; FIXME: This is not a valid way to emit this vid sequence: shift-right for -; division only works for non-negative numbers! +; We match this as a VID sequence (-3 / 8) + 5 but choose not to introduce +; division to compute it. define <16 x i8> @buildvec_not_vid_v16i8() { ; CHECK-LABEL: buildvec_not_vid_v16i8: ; CHECK: # %bb.0: +; CHECK-NEXT: li a0, 3 ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu -; CHECK-NEXT: vid.v v8 -; CHECK-NEXT: li a0, -3 -; CHECK-NEXT: vmul.vx v8, v8, a0 -; CHECK-NEXT: vsrl.vi v8, v8, 3 -; CHECK-NEXT: vadd.vi v8, v8, 5 +; CHECK-NEXT: vmv.s.x v9, a0 +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: vsetivli zero, 7, e8, m1, tu, mu +; CHECK-NEXT: vslideup.vi v8, v9, 6 ; CHECK-NEXT: ret ret <16 x i8> } -- 2.7.4