From 3e457f505e69286ab5d0c7980deab0302cc32def Mon Sep 17 00:00:00 2001 From: Reed Kotler Date: Tue, 19 Feb 2013 03:56:57 +0000 Subject: [PATCH] Expand pseudos/macros BteqzT8SltiX16, BteqzT8SltiuX16, BtnezT8SltiX16, BtnezT8SltiuX16 . llvm-svn: 175486 --- llvm/lib/Target/Mips/Mips16InstrInfo.cpp | 17 +++++- llvm/lib/Target/Mips/Mips16InstrInfo.td | 32 +++++++++++ llvm/test/CodeGen/Mips/selgek.ll | 92 ++++++++++++++++++++++++++++++++ llvm/test/CodeGen/Mips/selltk.ll | 92 ++++++++++++++++++++++++++++++++ 4 files changed, 232 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/Mips/selgek.ll create mode 100644 llvm/test/CodeGen/Mips/selltk.ll diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp index b619439..22cb963 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.cpp @@ -132,7 +132,6 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { MachineBasicBlock &MBB = *MI->getParent(); - switch(MI->getDesc().getOpcode()) { default: return false; @@ -146,11 +145,19 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::BteqzT8SltX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltRxRy16); break; + case Mips::BteqzT8SltiX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16, + Mips::SltiRxImm16, Mips::SltiRxImmX16); + break; case Mips::BteqzT8SltuX16: // TBD: figure out a way to get this or remove the instruction // altogether. ExpandFEXT_T8I816_ins(MBB, MI, Mips::BteqzX16, Mips::SltuRxRy16); break; + case Mips::BteqzT8SltiuX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BteqzX16, + Mips::SltiuRxImm16, Mips::SltiuRxImmX16); + break; case Mips::BtnezT8CmpX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::CmpRxRy16); break; @@ -161,11 +168,19 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const { case Mips::BtnezT8SltX16: ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltRxRy16); break; + case Mips::BtnezT8SltiX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16, + Mips::SltiRxImm16, Mips::SltiRxImmX16); + break; case Mips::BtnezT8SltuX16: // TBD: figure out a way to get this or remove the instruction // altogether. ExpandFEXT_T8I816_ins(MBB, MI, Mips::BtnezX16, Mips::SltuRxRy16); break; + case Mips::BtnezT8SltiuX16: + ExpandFEXT_T8I8I16_ins(MBB, MI, Mips::BtnezX16, + Mips::SltiuRxImm16, Mips::SltiuRxImmX16); + break; case Mips::RetRA16: ExpandRetRA16(MBB, MI, Mips::JrcRa16); break; diff --git a/llvm/lib/Target/Mips/Mips16InstrInfo.td b/llvm/lib/Target/Mips/Mips16InstrInfo.td index 1a5c30b..0d90df4 100644 --- a/llvm/lib/Target/Mips/Mips16InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips16InstrInfo.td @@ -1012,13 +1012,45 @@ def SllX16: FEXT_SHIFT16_ins<0b00, "sll", IIAlu>; // def SllvRxRy16 : FRxRxRy16_ins<0b00100, "sllv", IIAlu>; +// Format: SLTI rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate +// To record the result of a less-than comparison with a constant. +// +// +def SltiRxImm16: FRI16_ins<0b01010, "slti", IIAlu> { + let Defs = [T8]; +} + // // Format: SLTI rx, immediate MIPS16e // Purpose: Set on Less Than Immediate (Extended) // To record the result of a less-than comparison with a constant. // +// +def SltiRxImmX16: FEXT_RI16_ins<0b01010, "slti", IIAlu> { + let Defs = [T8]; +} + def SltiCCRxImmX16: FEXT_CCRXI16_ins<"slti">; +// Format: SLTIU rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate Unsigned +// To record the result of a less-than comparison with a constant. +// +// +def SltiuRxImm16: FRI16_ins<0b01011, "sltiu", IIAlu> { + let Defs = [T8]; +} + +// +// Format: SLTI rx, immediate MIPS16e +// Purpose: Set on Less Than Immediate Unsigned (Extended) +// To record the result of a less-than comparison with a constant. +// +// +def SltiuRxImmX16: FEXT_RI16_ins<0b01011, "sltiu", IIAlu> { + let Defs = [T8]; +} // // Format: SLTIU rx, immediate MIPS16e // Purpose: Set on Less Than Immediate Unsigned (Extended) diff --git a/llvm/test/CodeGen/Mips/selgek.ll b/llvm/test/CodeGen/Mips/selgek.ll new file mode 100644 index 0000000..0574d0d --- /dev/null +++ b/llvm/test/CodeGen/Mips/selgek.ll @@ -0,0 +1,92 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 2, align 4 +@b = global i32 1000, align 4 +@c = global i32 2, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp sge i32 %0, 1000 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %1 = load i32* @f, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %2 = load i32* @t, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %3 = load i32* @b, align 4 + %cmp1 = icmp sge i32 %3, 1 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %4 = load i32* @t, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %5 = load i32* @f, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %6 = load i32* @c, align 4 + %cmp6 = icmp sge i32 %6, 2 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %7 = load i32* @t, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %8 = load i32* @f, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %9 = load i32* @a, align 4 + %cmp11 = icmp sge i32 %9, 2 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %10 = load i32* @t, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %11 = load i32* @f, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: slti ${{[0-9]+}}, 1000 +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 1 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 2 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 2 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} diff --git a/llvm/test/CodeGen/Mips/selltk.ll b/llvm/test/CodeGen/Mips/selltk.ll new file mode 100644 index 0000000..e0b2af2 --- /dev/null +++ b/llvm/test/CodeGen/Mips/selltk.ll @@ -0,0 +1,92 @@ +; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16 + +@t = global i32 10, align 4 +@f = global i32 199, align 4 +@a = global i32 2, align 4 +@b = global i32 1000, align 4 +@c = global i32 2, align 4 +@z1 = common global i32 0, align 4 +@z2 = common global i32 0, align 4 +@z3 = common global i32 0, align 4 +@z4 = common global i32 0, align 4 +@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1 + +define void @calc_selltk() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" { +entry: + %0 = load i32* @a, align 4 + %cmp = icmp slt i32 %0, 1000 + br i1 %cmp, label %cond.true, label %cond.false + +cond.true: ; preds = %entry + %1 = load i32* @t, align 4 + br label %cond.end + +cond.false: ; preds = %entry + %2 = load i32* @f, align 4 + br label %cond.end + +cond.end: ; preds = %cond.false, %cond.true + %cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ] + store i32 %cond, i32* @z1, align 4 + %3 = load i32* @b, align 4 + %cmp1 = icmp slt i32 %3, 2 + br i1 %cmp1, label %cond.true2, label %cond.false3 + +cond.true2: ; preds = %cond.end + %4 = load i32* @f, align 4 + br label %cond.end4 + +cond.false3: ; preds = %cond.end + %5 = load i32* @t, align 4 + br label %cond.end4 + +cond.end4: ; preds = %cond.false3, %cond.true2 + %cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ] + store i32 %cond5, i32* @z2, align 4 + %6 = load i32* @c, align 4 + %cmp6 = icmp sgt i32 %6, 2 + br i1 %cmp6, label %cond.true7, label %cond.false8 + +cond.true7: ; preds = %cond.end4 + %7 = load i32* @f, align 4 + br label %cond.end9 + +cond.false8: ; preds = %cond.end4 + %8 = load i32* @t, align 4 + br label %cond.end9 + +cond.end9: ; preds = %cond.false8, %cond.true7 + %cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ] + store i32 %cond10, i32* @z3, align 4 + %9 = load i32* @a, align 4 + %cmp11 = icmp sgt i32 %9, 2 + br i1 %cmp11, label %cond.true12, label %cond.false13 + +cond.true12: ; preds = %cond.end9 + %10 = load i32* @f, align 4 + br label %cond.end14 + +cond.false13: ; preds = %cond.end9 + %11 = load i32* @t, align 4 + br label %cond.end14 + +cond.end14: ; preds = %cond.false13, %cond.true12 + %cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ] + store i32 %cond15, i32* @z4, align 4 + ret void +} + +attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" } +attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" } + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slt ${{[0-9]+}}, ${{[0-9]+}} +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 3 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} + +; 16: slti ${{[0-9]+}}, 3 # 16 bit inst +; 16: btnez $BB{{[0-9]+}}_{{[0-9]}} -- 2.7.4