From 3e06eafc2089f4c8ebca4ce632a29161d3a15df1 Mon Sep 17 00:00:00 2001 From: Michael Kuperstein Date: Wed, 28 Sep 2016 06:13:58 +0000 Subject: [PATCH] [DAG] Remove isVectorClearMaskLegal() check from vector_build dagcombine This check currently doesn't seem to do anything useful on any in-tree target: On non-x86, it always evaluates to false, so we never hit the code path that creates the shuffle with zero. On x86, it just forwards to isShuffleMaskLegal(), which is a reasonable thing to query in general, but doesn't make sense if only restricted to zero blends. Differential Revision: https://reviews.llvm.org/D24625 llvm-svn: 282567 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 7 ------- llvm/test/CodeGen/AMDGPU/r600-export-fix.ll | 4 ++-- llvm/test/CodeGen/SystemZ/vec-perm-13.ll | 4 ++-- 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index bd88287..d6f6185 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -13064,13 +13064,6 @@ SDValue DAGCombiner::reduceBuildVecToShuffle(SDNode *N) { Mask[i] = Vec2Offset + ExtIndex; } - // Avoid introducing illegal shuffles with zero. - // TODO: This doesn't actually do anything smart at the moment. - // We should either delete this, or check legality for all the shuffles - // we create. - if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT)) - return SDValue(); - // The type the input vectors may have changed above. InVT1 = VecIn1.getValueType(); diff --git a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll index 7d86f9e..665feeb 100644 --- a/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll +++ b/llvm/test/CodeGen/AMDGPU/r600-export-fix.ll @@ -3,9 +3,9 @@ ;CHECK: EXPORT T{{[0-9]}}.XYZW ;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000 -;CHECK: EXPORT T{{[0-9]}}.0XYZ +;CHECK: EXPORT T{{[0-9]}}.0YZW ;CHECK: EXPORT T{{[0-9]}}.XYZW -;CHECK: EXPORT T{{[0-9]}}.YZ00 +;CHECK: EXPORT T{{[0-9]}}.XY00 ;CHECK: EXPORT T{{[0-9]}}.0000 ;CHECK: EXPORT T{{[0-9]}}.0000 diff --git a/llvm/test/CodeGen/SystemZ/vec-perm-13.ll b/llvm/test/CodeGen/SystemZ/vec-perm-13.ll index 708d8de..d4aeffc 100644 --- a/llvm/test/CodeGen/SystemZ/vec-perm-13.ll +++ b/llvm/test/CodeGen/SystemZ/vec-perm-13.ll @@ -19,8 +19,8 @@ define <4 x i16> @f1(<4 x i16> %x) { ; CHECK-VECTOR-NEXT: .space 1 ; CHECK-VECTOR-NEXT: .byte 6 ; CHECK-VECTOR-NEXT: .byte 7 -; CHECK-VECTOR-NEXT: .byte 16 -; CHECK-VECTOR-NEXT: .byte 17 +; CHECK-VECTOR-NEXT: .byte 22 +; CHECK-VECTOR-NEXT: .byte 23 ; CHECK-VECTOR-NEXT: .space 1 ; CHECK-VECTOR-NEXT: .space 1 ; CHECK-VECTOR-NEXT: .space 1 -- 2.7.4