From 3decb52c8223b37a30d09d23ed3ecc398a14d971 Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Mon, 15 Mar 2021 13:33:29 +0000 Subject: [PATCH] aco: use uadd32_sat() helper for nir_op_uadd_sat MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Rhys Perry Reviewed-by: Timur Kristóf Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 6f7d9b3..cbce772 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -1721,21 +1721,7 @@ void visit_alu_instr(isel_context *ctx, nir_alu_instr *instr) } add_instr->vop3().clamp = 1; } else if (dst.regClass() == v1) { - if (ctx->options->chip_class >= GFX9) { - aco_ptr add{create_instruction(aco_opcode::v_add_u32, asVOP3(Format::VOP2), 2, 1)}; - add->operands[0] = Operand(src0); - add->operands[1] = Operand(src1); - add->definitions[0] = Definition(dst); - add->clamp = 1; - ctx->block->instructions.emplace_back(std::move(add)); - } else { - if (src1.regClass() != v1) - std::swap(src0, src1); - assert(src1.regClass() == v1); - Temp tmp = bld.tmp(v1); - Temp carry = bld.vadd32(Definition(tmp), src0, src1, true).def(1).getTemp(); - bld.vop2_e64(aco_opcode::v_cndmask_b32, Definition(dst), tmp, Operand((uint32_t) -1), carry); - } + uadd32_sat(bld, Definition(dst), src0, src1); } else { isel_err(&instr->instr, "Unimplemented NIR instr bit size"); } -- 2.7.4