From 3d4276f053061933d45140b7bcb727d6b6efc7b4 Mon Sep 17 00:00:00 2001 From: Eric Christopher Date: Tue, 27 Jan 2015 07:31:29 +0000 Subject: [PATCH] The subtarget is cached on the MachineFunction. Access it directly. llvm-svn: 227173 --- llvm/lib/CodeGen/EarlyIfConversion.cpp | 12 +++++------- llvm/lib/CodeGen/IfConversion.cpp | 12 +++++------- llvm/lib/CodeGen/MachineCombiner.cpp | 3 +-- llvm/lib/CodeGen/MachineScheduler.cpp | 4 +--- llvm/lib/CodeGen/MachineTraceMetrics.cpp | 7 +++---- llvm/lib/CodeGen/PostRASchedulerList.cpp | 4 +--- llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp | 3 +-- llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp | 3 +-- 8 files changed, 18 insertions(+), 30 deletions(-) diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp index 995606f..8f74271 100644 --- a/llvm/lib/CodeGen/EarlyIfConversion.cpp +++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp @@ -777,15 +777,13 @@ bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n" << "********** Function: " << MF.getName() << '\n'); // Only run if conversion if the target wants it. - if (!MF.getTarget() - .getSubtarget() - .enableEarlyIfConversion()) + const TargetSubtargetInfo &STI = MF.getSubtarget(); + if (!STI.enableEarlyIfConversion()) return false; - TII = MF.getSubtarget().getInstrInfo(); - TRI = MF.getSubtarget().getRegisterInfo(); - SchedModel = - MF.getTarget().getSubtarget().getSchedModel(); + TII = STI.getInstrInfo(); + TRI = STI.getRegisterInfo(); + SchedModel = STI.getSchedModel(); MRI = &MF.getRegInfo(); DomTree = &getAnalysis(); Loops = getAnalysisIfAvailable(); diff --git a/llvm/lib/CodeGen/IfConversion.cpp b/llvm/lib/CodeGen/IfConversion.cpp index e84d25d..7a29569 100644 --- a/llvm/lib/CodeGen/IfConversion.cpp +++ b/llvm/lib/CodeGen/IfConversion.cpp @@ -271,15 +271,13 @@ INITIALIZE_PASS_DEPENDENCY(MachineBranchProbabilityInfo) INITIALIZE_PASS_END(IfConverter, "if-converter", "If Converter", false, false) bool IfConverter::runOnMachineFunction(MachineFunction &MF) { - TLI = MF.getSubtarget().getTargetLowering(); - TII = MF.getSubtarget().getInstrInfo(); - TRI = MF.getSubtarget().getRegisterInfo(); + const TargetSubtargetInfo &ST = MF.getSubtarget(); + TLI = ST.getTargetLowering(); + TII = ST.getInstrInfo(); + TRI = ST.getRegisterInfo(); MBFI = &getAnalysis(); MBPI = &getAnalysis(); MRI = &MF.getRegInfo(); - - const TargetSubtargetInfo &ST = - MF.getTarget().getSubtarget(); SchedModel.init(ST.getSchedModel(), &ST, TII); if (!TII) return false; @@ -290,7 +288,7 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { if (!PreRegAlloc) { // Tail merge tend to expose more if-conversion opportunities. BranchFolder BF(true, false, *MBFI, *MBPI); - BFChange = BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(), + BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo(), getAnalysisIfAvailable()); } diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp index 2931258..7f03a17 100644 --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -406,8 +406,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) { } bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) { - const TargetSubtargetInfo &STI = - MF.getTarget().getSubtarget(); + const TargetSubtargetInfo &STI = MF.getSubtarget(); TII = STI.getInstrInfo(); TRI = STI.getRegisterInfo(); SchedModel = STI.getSchedModel(); diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index a554254..89ac6a8 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -336,9 +336,7 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) { if (skipOptnoneFunction(*mf.getFunction())) return false; - const TargetSubtargetInfo &ST = - mf.getTarget().getSubtarget(); - if (!ST.enablePostMachineScheduler()) { + if (!mf.getSubtarget().enablePostMachineScheduler()) { DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n"); return false; } diff --git a/llvm/lib/CodeGen/MachineTraceMetrics.cpp b/llvm/lib/CodeGen/MachineTraceMetrics.cpp index 2cf87eb..8aacd1f 100644 --- a/llvm/lib/CodeGen/MachineTraceMetrics.cpp +++ b/llvm/lib/CodeGen/MachineTraceMetrics.cpp @@ -52,12 +52,11 @@ void MachineTraceMetrics::getAnalysisUsage(AnalysisUsage &AU) const { bool MachineTraceMetrics::runOnMachineFunction(MachineFunction &Func) { MF = &Func; - TII = MF->getSubtarget().getInstrInfo(); - TRI = MF->getSubtarget().getRegisterInfo(); + const TargetSubtargetInfo &ST = MF->getSubtarget(); + TII = ST.getInstrInfo(); + TRI = ST.getRegisterInfo(); MRI = &MF->getRegInfo(); Loops = &getAnalysis(); - const TargetSubtargetInfo &ST = - MF->getTarget().getSubtarget(); SchedModel.init(ST.getSchedModel(), &ST, TII); BlockInfo.resize(MF->getNumBlockIDs()); ProcResourceCycles.resize(MF->getNumBlockIDs() * diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 89e1d11..ad59fc9 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -282,9 +282,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { } else { // Check that post-RA scheduling is enabled for this target. // This may upgrade the AntiDepMode. - const TargetSubtargetInfo &ST = - Fn.getTarget().getSubtarget(); - if (!enablePostRAScheduler(ST, PassConfig->getOptLevel(), + if (!enablePostRAScheduler(Fn.getSubtarget(), PassConfig->getOptLevel(), AntiDepMode, CriticalPathRCs)) return false; } diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 54f53dc..78e0848 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -893,8 +893,7 @@ bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) { << "********** Function: " << MF.getName() << '\n'); TII = MF.getSubtarget().getInstrInfo(); TRI = MF.getSubtarget().getRegisterInfo(); - SchedModel = - MF.getTarget().getSubtarget().getSchedModel(); + SchedModel = MF.getSubtarget().getSchedModel(); MRI = &MF.getRegInfo(); DomTree = &getAnalysis(); Loops = getAnalysisIfAvailable(); diff --git a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp index 0c36e8f..076903e 100644 --- a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp +++ b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp @@ -121,8 +121,7 @@ bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &mf) { static_cast(MF->getSubtarget().getInstrInfo()); TRI = MF->getSubtarget().getRegisterInfo(); MRI = &MF->getRegInfo(); - const TargetSubtargetInfo &ST = - MF->getTarget().getSubtarget(); + const TargetSubtargetInfo &ST = MF->getSubtarget(); SchedModel.init(ST.getSchedModel(), &ST, TII); Traces = &getAnalysis(); -- 2.7.4