From 3d41a58eac132e43576eb3463c922a45a4ceca34 Mon Sep 17 00:00:00 2001 From: Jinsong Ji Date: Thu, 5 Dec 2019 03:17:48 +0000 Subject: [PATCH] [PowerPC][NFC] Rename ANDI(S)o8 to ANDI(S)8o Summary: This is found during https://reviews.llvm.org/D70758 All the other record forms are having suffix o at the end. ANDIo8 and ANDISo8 are the only two that put o before 8. This patch rename them to be consistent with others. Reviewers: #powerpc, hfinkel, nemanjai, lei, steven.zhang, echristo, jhibbits, joerg Reviewed By: jhibbits Subscribers: wuzish, hiraditya, kbarton, shchenz, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70928 --- llvm/lib/Target/PowerPC/P9InstrResources.td | 2 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 16 ++++++++-------- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 4 ++-- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 18 +++++++++--------- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 8 ++++---- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 2 +- .../PowerPC/convert-rr-to-ri-instrs-out-of-range.mir | 4 ++-- llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 12 ++++++------ llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir | 4 ++-- llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 4 ++-- .../CodeGen/PowerPC/peephole-miscompile-extswsli.mir | 6 +++--- llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir | 6 +++--- 13 files changed, 44 insertions(+), 44 deletions(-) diff --git a/llvm/lib/Target/PowerPC/P9InstrResources.td b/llvm/lib/Target/PowerPC/P9InstrResources.td index 7d3780f..7bb8364 100644 --- a/llvm/lib/Target/PowerPC/P9InstrResources.td +++ b/llvm/lib/Target/PowerPC/P9InstrResources.td @@ -130,7 +130,7 @@ def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C], (instregex "CMP(WI|LWI|W|LW)(8)?$"), (instregex "CMP(L)?D(I)?$"), (instregex "SUBF(I)?C(8)?(O)?$"), - (instregex "ANDI(S)?o(8)?$"), + (instregex "ANDI(S)?(8)?(o)?$"), (instregex "ADDC(8)?(O)?$"), (instregex "ADDIC(8)?(o)?$"), (instregex "ADD(8|4)(O)?(o)?$"), diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 1d1d6b8..aac92ec 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -2181,12 +2181,12 @@ class BitPermutationSelector { SDValue ANDIVal, ANDISVal; if (ANDIMask != 0) - ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64, + ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64, ExtendToInt64(VRot, dl), getI32Imm(ANDIMask, dl)), 0); if (ANDISMask != 0) - ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64, + ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64, ExtendToInt64(VRot, dl), getI32Imm(ANDISMask, dl)), 0); @@ -2330,10 +2330,10 @@ class BitPermutationSelector { SDValue ANDIVal, ANDISVal; if (ANDIMask != 0) - ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64, + ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDI8o, dl, MVT::i64, ExtendToInt64(Res, dl), getI32Imm(ANDIMask, dl)), 0); if (ANDISMask != 0) - ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64, + ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDIS8o, dl, MVT::i64, ExtendToInt64(Res, dl), getI32Imm(ANDISMask, dl)), 0); if (!ANDIVal) @@ -2623,7 +2623,7 @@ SDNode *IntegerCompareEliminator::tryLogicOpOfCompares(SDNode *N) { assert((NewOpc != -1 || !IsBitwiseNegate) && "No record form available for AND8/OR8/XOR8?"); WideOp = - SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDIo8 : NewOpc, dl, + SDValue(CurDAG->getMachineNode(NewOpc == -1 ? PPC::ANDI8o : NewOpc, dl, MVT::i64, MVT::Glue, LHS, RHS), 0); } @@ -4790,7 +4790,7 @@ void PPCDAGToDAGISel::Select(SDNode *N) { assert((InVT == MVT::i64 || InVT == MVT::i32) && "Invalid input type for ANDIo_1_EQ_BIT"); - unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo; + unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDI8o : PPC::ANDIo; SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue, N->getOperand(0), CurDAG->getTargetConstant(1, dl, InVT)), @@ -6304,8 +6304,8 @@ void PPCDAGToDAGISel::PeepholePPC64ZExt() { case PPC::ORI: NewOpcode = PPC::ORI8; break; case PPC::ORIS: NewOpcode = PPC::ORIS8; break; case PPC::AND: NewOpcode = PPC::AND8; break; - case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break; - case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break; + case PPC::ANDIo: NewOpcode = PPC::ANDI8o; break; + case PPC::ANDISo: NewOpcode = PPC::ANDIS8o; break; } // Note: During the replacement process, the nodes will be in an diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 057ecfb..b6ba591 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11624,7 +11624,7 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) { unsigned Opcode = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8 || MI.getOpcode() == PPC::ANDIo_1_GT_BIT8) - ? PPC::ANDIo8 + ? PPC::ANDI8o : PPC::ANDIo; bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT || MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8); diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index 4dcb279..0f9ab56 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -474,11 +474,11 @@ defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), // Logical ops with immediate. let Defs = [CR0] in { -def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), +def ANDI8o : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), "andi. $dst, $src1, $src2", IIC_IntGeneral, [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, isDOT; -def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), +def ANDIS8o : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2), "andis. $dst, $src1, $src2", IIC_IntGeneral, [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, isDOT; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index f5e2b47..4d52573 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1836,8 +1836,8 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, int NewOpC = -1; int MIOpC = MI->getOpcode(); - if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDIo8 || - MIOpC == PPC::ANDISo || MIOpC == PPC::ANDISo8) + if (MIOpC == PPC::ANDIo || MIOpC == PPC::ANDI8o || + MIOpC == PPC::ANDISo || MIOpC == PPC::ANDIS8o) NewOpC = MIOpC; else { NewOpC = PPC::getRecordFormOpcode(MIOpC); @@ -1945,7 +1945,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, Mask >>= MBInLoHWord ? 0 : 16; NewOpC = MIOpC == PPC::RLWINM ? (MBInLoHWord ? PPC::ANDIo : PPC::ANDISo) : - (MBInLoHWord ? PPC::ANDIo8 :PPC::ANDISo8); + (MBInLoHWord ? PPC::ANDI8o :PPC::ANDIS8o); } else if (MRI->use_empty(GPRRes) && (ME == 31) && (ME - MB + 1 == SH) && (MB >= 16)) { // If we are rotating by the exact number of bits as are in the mask @@ -1953,7 +1953,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, // that's just an andis. (as long as the GPR result has no uses). Mask = ((1LLU << 32) - 1) & ~((1LLU << (32 - SH)) - 1); Mask >>= 16; - NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDISo8; + NewOpC = MIOpC == PPC::RLWINM ? PPC::ANDISo :PPC::ANDIS8o; } // If we've set the mask, we can transform. if (Mask != ~0LLU) { @@ -1966,7 +1966,7 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg, int64_t MB = MI->getOperand(3).getImm(); if (MB >= 48) { uint64_t Mask = (1LLU << (63 - MB + 1)) - 1; - NewOpC = PPC::ANDIo8; + NewOpC = PPC::ANDI8o; MI->RemoveOperand(3); MI->getOperand(2).setImm(Mask); NumRcRotatesConvertedToRcAnd++; @@ -2306,7 +2306,7 @@ void PPCInstrInfo::replaceInstrWithLI(MachineInstr &MI, // Replace the instruction. if (LII.SetCR) { - MI.setDesc(get(LII.Is64Bit ? PPC::ANDIo8 : PPC::ANDIo)); + MI.setDesc(get(LII.Is64Bit ? PPC::ANDI8o : PPC::ANDIo)); // Set the immediate. MachineInstrBuilder(*MI.getParent()->getParent(), MI) .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine); @@ -3083,7 +3083,7 @@ bool PPCInstrInfo::instrHasImmForm(unsigned Opc, bool IsVFReg, switch(Opc) { default: llvm_unreachable("Unknown opcode"); case PPC::ANDo: III.ImmOpcode = PPC::ANDIo; break; - case PPC::AND8o: III.ImmOpcode = PPC::ANDIo8; break; + case PPC::AND8o: III.ImmOpcode = PPC::ANDI8o; break; case PPC::OR: III.ImmOpcode = PPC::ORI; break; case PPC::OR8: III.ImmOpcode = PPC::ORI8; break; case PPC::XOR: III.ImmOpcode = PPC::XORI; break; @@ -4067,8 +4067,8 @@ PPCInstrInfo::isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, case PPC::ORIS: case PPC::XORI: case PPC::XORIS: - case PPC::ANDIo8: - case PPC::ANDISo8: + case PPC::ANDI8o: + case PPC::ANDIS8o: case PPC::ORI8: case PPC::ORIS8: case PPC::XORI8: diff --git a/llvm/lib/Target/PowerPC/PPCInstrVSX.td b/llvm/lib/Target/PowerPC/PPCInstrVSX.td index 9d5db66..6af525f 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrVSX.td +++ b/llvm/lib/Target/PowerPC/PPCInstrVSX.td @@ -1961,7 +1961,7 @@ def VectorExtractions { - The order of elements after the move to GPR is reversed, so we invert the bits of the index prior to truncating to the range 0-7 */ - dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDIo8 $Idx, 8))); + dag BE_VBYTE_PERM_VEC = (v16i8 (LVSL ZERO8, (ANDI8o $Idx, 8))); dag BE_VBYTE_PERMUTE = (v16i8 (VPERM $S, $S, BE_VBYTE_PERM_VEC)); dag BE_MV_VBYTE = (MFVSRD (EXTRACT_SUBREG @@ -1980,7 +1980,7 @@ def VectorExtractions { the bits of the index prior to truncating to the range 0-3 */ dag BE_VHALF_PERM_VEC = (v16i8 (LVSL ZERO8, - (RLDICR (ANDIo8 $Idx, 4), 1, 62))); + (RLDICR (ANDI8o $Idx, 4), 1, 62))); dag BE_VHALF_PERMUTE = (v16i8 (VPERM $S, $S, BE_VHALF_PERM_VEC)); dag BE_MV_VHALF = (MFVSRD (EXTRACT_SUBREG @@ -1998,7 +1998,7 @@ def VectorExtractions { the bits of the index prior to truncating to the range 0-1 */ dag BE_VWORD_PERM_VEC = (v16i8 (LVSL ZERO8, - (RLDICR (ANDIo8 $Idx, 2), 2, 61))); + (RLDICR (ANDI8o $Idx, 2), 2, 61))); dag BE_VWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VWORD_PERM_VEC)); dag BE_MV_VWORD = (MFVSRD (EXTRACT_SUBREG @@ -2014,7 +2014,7 @@ def VectorExtractions { element indices. */ dag BE_VDWORD_PERM_VEC = (v16i8 (LVSL ZERO8, - (RLDICR (ANDIo8 $Idx, 1), 3, 60))); + (RLDICR (ANDI8o $Idx, 1), 3, 60))); dag BE_VDWORD_PERMUTE = (v16i8 (VPERM $S, $S, BE_VDWORD_PERM_VEC)); dag BE_VARIABLE_DWORD = (MFVSRD (EXTRACT_SUBREG diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index f42b4bc..e503e8a 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -908,7 +908,7 @@ bool PPCMIPeephole::simplifyCode(void) { MI.RemoveOperand(4); MI.RemoveOperand(3); MI.getOperand(2).setImm(0); - MI.setDesc(TII->get(Is64Bit ? PPC::ANDIo8 : PPC::ANDIo)); + MI.setDesc(TII->get(Is64Bit ? PPC::ANDI8o : PPC::ANDIo)); } Simplified = true; NumRotatesCollapsed++; diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir index a0c461f..bf006f7 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir @@ -1106,7 +1106,7 @@ body: | %0 = COPY $x3 %2 = LI 88 %3 = SLDo %0, killed %2, implicit-def $cr0 - ; CHECK: ANDIo8 %0, 0, implicit-def $cr0 + ; CHECK: ANDI8o %0, 0, implicit-def $cr0 ; CHECK-LATE: andi. 5, 3, 0 %4 = COPY killed $cr0 %5 = ISEL8 %1, %0, %4.sub_eq @@ -1212,7 +1212,7 @@ body: | %0 = COPY $x3 %2 = LI 64 %3 = SRDo %0, killed %2, implicit-def $cr0 - ; CHECK: ANDIo8 %0, 0, implicit-def $cr0 + ; CHECK: ANDI8o %0, 0, implicit-def $cr0 ; CHECK-LATE: andi. 5, 3, 0 %4 = COPY killed $cr0 %5 = ISEL8 %1, %0, %4.sub_eq diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir index 3401a421..18dfe9d 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir @@ -1498,7 +1498,7 @@ body: | %1 = LI8 321 %0 = COPY $x3 %2 = AND8o %1, %0, implicit-def $cr0 - ; CHECK: ANDIo8 %0, 321, implicit-def $cr0 + ; CHECK: ANDI8o %0, 321, implicit-def $cr0 ; CHECK-LATE: andi. 5, 3, 321 %3 = COPY killed $cr0 %4 = ISEL8 %1, %0, %3.sub_eq @@ -3928,7 +3928,7 @@ body: | %1 = COPY $x4 %0 = LI8 -1 %2 = RLDICLo %0, 53, 48, implicit-def $cr0 - ; CHECK: ANDIo8 %0, 65535 + ; CHECK: ANDI8o %0, 65535 ; CHECK-LATE: li 3, -1 ; CHECK-LATE: andi. 3, 3, 65535 %3 = COPY killed $cr0 @@ -3983,7 +3983,7 @@ body: | %0 = LI8 200 %2 = RLDICLo %0, 61, 3, implicit-def $cr0 ; CHECK: LI8 25 - ; CHECK: ANDIo8 %0, 25 + ; CHECK: ANDI8o %0, 25 ; CHECK-LATE-NOT: andi. %3 = COPY killed $cr0 %4 = ISEL8 %1, %2, %3.sub_eq @@ -4036,7 +4036,7 @@ body: | %1 = COPY $x4 %0 = LI8 2 %2 = RLDICLo %0, 32, 32, implicit-def $cr0 - ; CHECK: ANDIo8 %0, 0 + ; CHECK: ANDI8o %0, 0 ; CHECK-LATE: li 3, 2 ; CHECK-LATE: andi. 3, 3, 0 %3 = COPY killed $cr0 @@ -4365,7 +4365,7 @@ body: | %3 = LI -22 %4 = RLWINMo %3, 5, 24, 31, implicit-def $cr0 ; CHECK: LI -22 - ; CHECK-NOT: ANDIo8 %3, 65514 + ; CHECK-NOT: ANDI8o %3, 65514 ; CHECK-LATE-NOT: andi. %5 = COPY killed $cr0 %6 = ISEL %2, %3, %5.sub_eq @@ -4426,7 +4426,7 @@ body: | %0 = COPY $x3 %2 = LI8 -18 %3 = RLWINM8o %2, 4, 20, 27, implicit-def $cr0 - ; CHECK: ANDIo8 %2, 3808 + ; CHECK: ANDI8o %2, 3808 ; CHECK-LATE: li 3, -18 ; CHECK-LATE: andi. 3, 3, 3808 %7 = COPY killed $cr0 diff --git a/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir b/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir index bf8ce2b..5f52bde 100644 --- a/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir +++ b/llvm/test/CodeGen/PowerPC/ifcvt-diamond-ret.mir @@ -6,7 +6,7 @@ body: | liveins: $x0, $x3 successors: %bb.1(0x40000000), %bb.2(0x40000000) - dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt + dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt $cr2lt = CROR $cr0gt, $cr0gt BCn killed renamable $cr2lt, %bb.2 B %bb.1 @@ -26,7 +26,7 @@ body: | # CHECK: body: | # CHECK: bb.0: -# CHECK: dead renamable $x3 = ANDIo8 killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt +# CHECK: dead renamable $x3 = ANDI8o killed renamable $x3, 1, implicit-def dead $cr0, implicit-def $cr0gt # CHECK: $cr2lt = CROR $cr0gt, $cr0gt # CHECK: renamable $x3 = LIS8 4096 # CHECK: MTLR8 $x0, implicit-def $lr8 diff --git a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll index a247be7..fac7522 100644 --- a/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll +++ b/llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll @@ -7,11 +7,11 @@ define signext i32 @fn1(i32 %baz) { %2 = zext i32 %1 to i64 %3 = shl i64 %2, 48 %4 = ashr exact i64 %3, 48 -; CHECK: ANDIo8 killed {{[^,]+}}, 65520, implicit-def dead $cr0 +; CHECK: ANDI8o killed {{[^,]+}}, 65520, implicit-def dead $cr0 ; CHECK: CMPLDI ; CHECK: BCC -; CHECK: ANDIo8 {{[^,]+}}, 65520, implicit-def $cr0 +; CHECK: ANDI8o {{[^,]+}}, 65520, implicit-def $cr0 ; CHECK: COPY $cr0 ; CHECK: BCC %5 = icmp eq i64 %4, 0 diff --git a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir index 9f50a07..54bc7cd 100644 --- a/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir +++ b/llvm/test/CodeGen/PowerPC/peephole-miscompile-extswsli.mir @@ -14,14 +14,14 @@ body: | ; CHECK: [[COPY1:%[0-9]+]]:g8rc = COPY $x5 ; CHECK: [[COPY2:%[0-9]+]]:g8rc = COPY $x4 ; CHECK: [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3 - ; CHECK: [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0 + ; CHECK: [[ANDI8o_:%[0-9]+]]:g8rc = ANDI8o [[COPY1]], 1, implicit-def $cr0 ; CHECK: [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt ; CHECK: BCn killed [[COPY4]], %bb.2 ; CHECK: B %bb.1 ; CHECK: bb.1: ; CHECK: liveins: $x3 ; CHECK: [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3 - ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61 + ; CHECK: [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDI8o_]], 2, 61 ; CHECK: $x3 = COPY [[RLDICR]] ; CHECK: [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61 ; CHECK: [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]] @@ -41,7 +41,7 @@ body: | %3:g8rc = COPY $x5 %2:g8rc = COPY $x4 %1:g8rc_and_g8rc_nox0 = COPY $x3 - %11:g8rc = ANDIo8 %3, 1, implicit-def $cr0 + %11:g8rc = ANDI8o %3, 1, implicit-def $cr0 %6:crbitrc = COPY $cr0gt BCn killed %6, %bb.2 B %bb.1 diff --git a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir index 95ee0a5..1632e64 100644 --- a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir +++ b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir @@ -297,7 +297,7 @@ body: | %0:g8rc = LI8 -11 %2:g8rc_and_g8rc_nox0 = RLDICLo %0, 2, 49, implicit-def $cr0 ; CHECK: LI8 32727 - ; CHECK: ANDIo8 %0, 32727 + ; CHECK: ANDI8o %0, 32727 ; CHECK-LATE-NOT: andi. ; CHECK-LATE: rldicl. %3:crrc = COPY killed $cr0 @@ -351,7 +351,7 @@ body: | %0:g8rc_and_g8rc_nox0 = LI8 1 %2:g8rc = RLDICLo %0, 32, 33, implicit-def $cr0 ; CHECK: LI8 1 - ; CHECK: ANDIo8 %0, 0 + ; CHECK: ANDI8o %0, 0 ; CHECK-LATE: li [[IMM:[0-9]+]], 1 ; CHECK-LATE: andi. {{[0-9]+}}, [[IMM]], 0 %3:crrc = COPY killed $cr0 @@ -405,7 +405,7 @@ body: | %0:g8rc_and_g8rc_nox0 = LI8 -11 %2:g8rc = RLDICLo %0, 2, 49, implicit-def $cr0 ; CHECK: LI8 -11 - ; CHECK: ANDIo8 %0, 65525 + ; CHECK: ANDI8o %0, 65525 ; CHECK-LATE-NOT: andi. ; CHECK-LATE: rldicl. %3:crrc = COPY killed $cr0 -- 2.7.4