From 3cc69021e5d4e4fe5322d425f4abf8128f0599b7 Mon Sep 17 00:00:00 2001 From: Graham Sider Date: Thu, 21 Apr 2022 10:32:02 -0400 Subject: [PATCH] drm/amdgpu: Implement get_vmid_pasid_mapping for gfx11 Implement gmc_v11_0_get_vmid_pasid_mapping_info to fix gmc_v11_0_flush_gpu_tlb_pasid logic. Change from gfx10 to use IH_VMID_*_LUT registers for VMID -> PASID mapping. Signed-off-by: Graham Sider Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 8d733eeac556..477f67d9b07c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -155,21 +155,13 @@ static bool gmc_v11_0_use_invalidate_semaphore(struct amdgpu_device *adev, (!amdgpu_sriov_vf(adev))); } -static bool gmc_v11_0_get_atc_vmid_pasid_mapping_info( +static bool gmc_v11_0_get_vmid_pasid_mapping_info( struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid) { -#if 0 // TODO: - uint32_t value; + *p_pasid = RREG32(SOC15_REG_OFFSET(OSSSYS, 0, regIH_VMID_0_LUT) + vmid) & 0xffff; - value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING) - + vmid); - *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK; - - return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK); -#else - return 0; -#endif + return !!(*p_pasid); } /* @@ -340,7 +332,7 @@ static int gmc_v11_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev, for (vmid = 1; vmid < 16; vmid++) { - ret = gmc_v11_0_get_atc_vmid_pasid_mapping_info(adev, vmid, + ret = gmc_v11_0_get_vmid_pasid_mapping_info(adev, vmid, &queried_pasid); if (ret && queried_pasid == pasid) { if (all_hub) { -- 2.34.1