From 3cbc0a07f92b4a630a1c03a6587d52f206ec8248 Mon Sep 17 00:00:00 2001 From: Roman Lebedev Date: Sun, 3 Oct 2021 23:37:22 +0300 Subject: [PATCH] [X86][Costmodel] Load/store i16 Stride=3 VF=16 interleaving costs The only sched models that for cpu's that support avx2 but not avx512 are: haswell, broadwell, skylake, zen1-3 For load we have: https://godbolt.org/z/1T6MMzeh3 - for intels `Block RThroughput: =28.0`; for ryzens, `Block RThroughput: <=8.5` So pick cost of `28`. For store we have: https://godbolt.org/z/1T6MMzeh3 - for intels `Block RThroughput: <=27.0`; for ryzens, `Block RThroughput: <=7.0` So pick cost of `27`. I'm directly using the shuffling asm the llc produced, without any manual fixups that may be needed to ensure sequential execution. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D111017 --- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 2 ++ llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll | 2 +- llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index a6654ed..45eb4b2 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -5103,6 +5103,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {3, MVT::v2i16, 5}, // (load 6i16 and) deinterleave into 3 x 2i16 {3, MVT::v4i16, 7}, // (load 12i16 and) deinterleave into 3 x 4i16 {3, MVT::v8i16, 9}, // (load 24i16 and) deinterleave into 3 x 8i16 + {3, MVT::v16i16, 28}, // (load 48i16 and) deinterleave into 3 x 16i16 {3, MVT::v8i32, 17}, // (load 24i32 and) deinterleave into 3 x 8i32 @@ -5165,6 +5166,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCostAVX2( {3, MVT::v2i16, 4}, // interleave 3 x 2i16 into 6i16 (and store) {3, MVT::v4i16, 6}, // interleave 3 x 4i16 into 12i16 (and store) {3, MVT::v8i16, 12}, // interleave 3 x 8i16 into 24i16 (and store) + {3, MVT::v16i16, 27}, // interleave 3 x 16i16 into 48i16 (and store) {4, MVT::v2i8, 4}, // interleave 4 x 2i8 into 8i8 (and store) {4, MVT::v4i8, 4}, // interleave 4 x 4i8 into 16i8 (and store) diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll index bd2a145..4c72a9d 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll @@ -29,7 +29,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 8 for VF 2 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 10 for VF 4 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 11 for VF 8 For instruction: %v0 = load i16, i16* %in0, align 2 -; AVX2: LV: Found an estimated cost of 129 for VF 16 For instruction: %v0 = load i16, i16* %in0, align 2 +; AVX2: LV: Found an estimated cost of 31 for VF 16 For instruction: %v0 = load i16, i16* %in0, align 2 ; AVX2: LV: Found an estimated cost of 258 for VF 32 For instruction: %v0 = load i16, i16* %in0, align 2 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: %v0 = load i16, i16* %in0, align 2 diff --git a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll index 3ab2709..74246c8 100644 --- a/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll +++ b/llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll @@ -29,7 +29,7 @@ target triple = "x86_64-unknown-linux-gnu" ; AVX2: LV: Found an estimated cost of 7 for VF 2 For instruction: store i16 %v2, i16* %out2, align 2 ; AVX2: LV: Found an estimated cost of 9 for VF 4 For instruction: store i16 %v2, i16* %out2, align 2 ; AVX2: LV: Found an estimated cost of 14 for VF 8 For instruction: store i16 %v2, i16* %out2, align 2 -; AVX2: LV: Found an estimated cost of 129 for VF 16 For instruction: store i16 %v2, i16* %out2, align 2 +; AVX2: LV: Found an estimated cost of 30 for VF 16 For instruction: store i16 %v2, i16* %out2, align 2 ; AVX2: LV: Found an estimated cost of 258 for VF 32 For instruction: store i16 %v2, i16* %out2, align 2 ; ; AVX512: LV: Found an estimated cost of 1 for VF 1 For instruction: store i16 %v2, i16* %out2, align 2 -- 2.7.4