From 3c6459285c8423543713a1b579199f5f351814de Mon Sep 17 00:00:00 2001 From: "danno@chromium.org" Date: Wed, 8 Feb 2012 14:41:10 +0000 Subject: [PATCH] MIPS: Don't allow large immediates for certain instructions. Some instructions can use >16 bit immediates if they represent a <=16 bit signed value. However some logical instructions (andi, xori, ori, lui) should always treat the immediate value as unsigned. This patch adds an ASSERT to these places and a minor change to MacroAssembler::li to satisfy this. BUG= TEST= Review URL: https://chromiumcodereview.appspot.com/9309077 Patch from Daniel Kalmar . git-svn-id: http://v8.googlecode.com/svn/branches/bleeding_edge@10644 ce2b1a6d-e550-0410-aec6-3dcde31c8c00 --- src/mips/assembler-mips.cc | 4 ++++ src/mips/macro-assembler-mips.cc | 8 ++++---- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc index 85b6ed8..9f803d9 100644 --- a/src/mips/assembler-mips.cc +++ b/src/mips/assembler-mips.cc @@ -1245,6 +1245,7 @@ void Assembler::and_(Register rd, Register rs, Register rt) { void Assembler::andi(Register rt, Register rs, int32_t j) { + ASSERT(is_uint16(j)); GenInstrImmediate(ANDI, rs, rt, j); } @@ -1255,6 +1256,7 @@ void Assembler::or_(Register rd, Register rs, Register rt) { void Assembler::ori(Register rt, Register rs, int32_t j) { + ASSERT(is_uint16(j)); GenInstrImmediate(ORI, rs, rt, j); } @@ -1265,6 +1267,7 @@ void Assembler::xor_(Register rd, Register rs, Register rt) { void Assembler::xori(Register rt, Register rs, int32_t j) { + ASSERT(is_uint16(j)); GenInstrImmediate(XORI, rs, rt, j); } @@ -1445,6 +1448,7 @@ void Assembler::swr(Register rd, const MemOperand& rs) { void Assembler::lui(Register rd, int32_t j) { + ASSERT(is_uint16(j)); GenInstrImmediate(LUI, zero_reg, rd, j); } diff --git a/src/mips/macro-assembler-mips.cc b/src/mips/macro-assembler-mips.cc index 678b8b1..f559d71 100644 --- a/src/mips/macro-assembler-mips.cc +++ b/src/mips/macro-assembler-mips.cc @@ -771,18 +771,18 @@ void MacroAssembler::li(Register rd, Operand j, bool gen2instr) { } else if (!(j.imm32_ & kHiMask)) { ori(rd, zero_reg, j.imm32_); } else if (!(j.imm32_ & kImm16Mask)) { - lui(rd, (j.imm32_ & kHiMask) >> kLuiShift); + lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask); } else { - lui(rd, (j.imm32_ & kHiMask) >> kLuiShift); + lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask); ori(rd, rd, (j.imm32_ & kImm16Mask)); } } else if (MustUseReg(j.rmode_) || gen2instr) { if (MustUseReg(j.rmode_)) { RecordRelocInfo(j.rmode_, j.imm32_); } - // We need always the same number of instructions as we may need to patch + // We always need the same number of instructions as we may need to patch // this code to load another value which may need 2 instructions to load. - lui(rd, (j.imm32_ & kHiMask) >> kLuiShift); + lui(rd, (j.imm32_ >> kLuiShift) & kImm16Mask); ori(rd, rd, (j.imm32_ & kImm16Mask)); } } -- 2.7.4