From 3c0d81d43fd75ca89fdf59c4887afe6908ffb35e Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Wed, 17 May 2023 14:15:02 +0100 Subject: [PATCH] [AMDGPU] Simplify scavenging in indirectCopyToAGPR This just makes it clearer that we do not want the scavenger to spill here. NFCI. Differential Revision: https://reviews.llvm.org/D150774 --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index a38a835..6ecc848 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -634,11 +634,11 @@ static void indirectCopyToAGPR(const SIInstrInfo &TII, assert(MBB.getParent()->getRegInfo().isReserved(Tmp) && "VGPR used for an intermediate copy should have been reserved."); - // Only loop through if there are any free registers left, otherwise - // scavenger may report a fatal error without emergency spill slot - // or spill with the slot. - while (RegNo-- && RS.FindUnusedReg(&AMDGPU::VGPR_32RegClass)) { - Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0); + // Only loop through if there are any free registers left. We don't want to + // spill. + while (RegNo--) { + Register Tmp2 = RS.scavengeRegister(&AMDGPU::VGPR_32RegClass, 0, + /* AllowSpill */ false); if (!Tmp2 || RI.getHWRegIndex(Tmp2) >= MaxVGPRs) break; Tmp = Tmp2; @@ -7919,9 +7919,10 @@ MachineInstrBuilder SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB, return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e32), DestReg); // If available, prefer to use vcc. - Register UnusedCarry = !RS.isRegUsed(AMDGPU::VCC) - ? Register(RI.getVCC()) - : RS.scavengeRegister(RI.getBoolRC(), I, 0, false); + Register UnusedCarry = + !RS.isRegUsed(AMDGPU::VCC) + ? Register(RI.getVCC()) + : RS.scavengeRegister(RI.getBoolRC(), I, 0, /* AllowSpill */ false); // TODO: Users need to deal with this. if (!UnusedCarry.isValid()) -- 2.7.4