From 3c06617f0e1dbef3886066bd83618670e40c7311 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Thu, 19 Apr 2018 11:37:26 +0000 Subject: [PATCH] [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides. These are all already handled identically by WriteFMA. llvm-svn: 330319 --- llvm/lib/Target/X86/X86SchedBroadwell.td | 9 --------- llvm/lib/Target/X86/X86SchedHaswell.td | 4 +--- llvm/lib/Target/X86/X86SchedSkylakeClient.td | 4 ---- llvm/lib/Target/X86/X86SchedSkylakeServer.td | 9 --------- 4 files changed, 1 insertion(+), 25 deletions(-) diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td index 9c178bb..fba3964 100755 --- a/llvm/lib/Target/X86/X86SchedBroadwell.td +++ b/llvm/lib/Target/X86/X86SchedBroadwell.td @@ -1087,15 +1087,6 @@ def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr", "(V?)RSQRTPSr", "(V?)RSQRTSSr")>; -def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> { - let Latency = 5; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[BWWriteResGroup48], - (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r", - "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>; - def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> { let Latency = 5; let NumMicroOps = 1; diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td index 32fec40..495ae29 100644 --- a/llvm/lib/Target/X86/X86SchedHaswell.td +++ b/llvm/lib/Target/X86/X86SchedHaswell.td @@ -2295,9 +2295,7 @@ def HWWriteResGroup90 : SchedWriteRes<[HWPort01]> { def: InstRW<[HWWriteResGroup90], (instregex "(V?)MULPD(Y?)rr", "(V?)MULPS(Y?)rr", "(V?)MULSDrr", - "(V?)MULSSrr", - "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r", - "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>; + "(V?)MULSSrr")>; def HWWriteResGroup91 : SchedWriteRes<[HWPort0,HWPort23]> { let Latency = 10; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index 06b3870..1d25b20 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -1078,10 +1078,6 @@ def: InstRW<[SKLWriteResGroup48], (instregex "(V?)ADDPD(Y?)rr", "(V?)SUBPS(Y?)rr", "(V?)SUBSDrr", "(V?)SUBSSrr")>; -def: InstRW<[SKLWriteResGroup48], - (instregex - "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r", - "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>; def SKLWriteResGroup50 : SchedWriteRes<[SKLPort5]> { let Latency = 4; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 196f6d9..9353955 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -2344,15 +2344,6 @@ def: InstRW<[SKXWriteResGroup50], (instregex "ADDPDrr", "VSUBSDrr", "VSUBSSZrr", "VSUBSSrr")>; -def: InstRW<[SKXWriteResGroup50], - (instregex - "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Yr", - "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Z128r", - "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Z256r", - "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Zr", - "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)r", - "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)Zr", - "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>; def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { let Latency = 4; -- 2.7.4