From 3bcfdfb06e2cd444a3ffe6b7cff560539970586c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 25 Aug 2022 08:41:05 +0200 Subject: [PATCH] radv: store binning settings into the physical device To avoid re-computing this every time. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 7 +++---- src/amd/vulkan/radv_device.c | 26 ++++++++++++++++++++++++++ src/amd/vulkan/radv_pipeline.c | 35 ++++------------------------------- src/amd/vulkan/radv_private.h | 16 ++++++++-------- 4 files changed, 41 insertions(+), 43 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index b189299..09b0699 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1401,16 +1401,15 @@ radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer) if (!cmd_buffer->device->pbb_allowed) return; - struct radv_binning_settings settings = - radv_get_binning_settings(cmd_buffer->device->physical_device); + struct radv_binning_settings *settings = &cmd_buffer->device->physical_device->binning_settings; bool break_for_new_ps = (!cmd_buffer->state.emitted_graphics_pipeline || cmd_buffer->state.emitted_graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT] != cmd_buffer->state.graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]) && - (settings.context_states_per_bin > 1 || settings.persistent_states_per_bin > 1); + (settings->context_states_per_bin > 1 || settings->persistent_states_per_bin > 1); bool break_for_new_cb_target_mask = (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) && - settings.context_states_per_bin > 1; + settings->context_states_per_bin > 1; if (!break_for_new_ps && !break_for_new_cb_target_mask) return; diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index a311e65..7ad0053 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -657,6 +657,31 @@ radv_physical_device_init_queue_table(struct radv_physical_device *pdevice) pdevice->num_queues = idx; } +static void +radv_get_binning_settings(const struct radv_physical_device *pdevice, + struct radv_binning_settings *settings) +{ + if (pdevice->rad_info.has_dedicated_vram) { + if (pdevice->rad_info.max_render_backends > 4) { + settings->context_states_per_bin = 1; + settings->persistent_states_per_bin = 1; + } else { + settings->context_states_per_bin = 3; + settings->persistent_states_per_bin = 8; + } + settings->fpovs_per_batch = 63; + } else { + /* The context states are affected by the scissor bug. */ + settings->context_states_per_bin = 6; + /* 32 causes hangs for RAVEN. */ + settings->persistent_states_per_bin = 16; + settings->fpovs_per_batch = 63; + } + + if (pdevice->rad_info.has_gfx9_scissor_bug) + settings->context_states_per_bin = 1; +} + static VkResult radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm_device, struct radv_physical_device **device_out) @@ -901,6 +926,7 @@ radv_physical_device_try_create(struct radv_instance *instance, drmDevicePtr drm ac_get_hs_info(&device->rad_info, &device->hs); ac_get_task_info(&device->rad_info, &device->task_info); + radv_get_binning_settings(device, &device->binning_settings); *device_out = device; diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 1d77be9..f169966 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -5128,33 +5128,6 @@ radv_pipeline_init_disabled_binning_state(struct radv_graphics_pipeline *pipelin pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0; } -struct radv_binning_settings -radv_get_binning_settings(const struct radv_physical_device *pdev) -{ - struct radv_binning_settings settings; - if (pdev->rad_info.has_dedicated_vram) { - if (pdev->rad_info.max_render_backends > 4) { - settings.context_states_per_bin = 1; - settings.persistent_states_per_bin = 1; - } else { - settings.context_states_per_bin = 3; - settings.persistent_states_per_bin = 8; - } - settings.fpovs_per_batch = 63; - } else { - /* The context states are affected by the scissor bug. */ - settings.context_states_per_bin = 6; - /* 32 causes hangs for RAVEN. */ - settings.persistent_states_per_bin = 16; - settings.fpovs_per_batch = 63; - } - - if (pdev->rad_info.has_gfx9_scissor_bug) - settings.context_states_per_bin = 1; - - return settings; -} - static void radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline, const struct radv_blend_state *blend, @@ -5174,17 +5147,17 @@ radv_pipeline_init_binning_state(struct radv_graphics_pipeline *pipeline, unreachable("Unhandled generation for binning bin size calculation"); if (device->pbb_allowed && bin_size.width && bin_size.height) { - struct radv_binning_settings settings = radv_get_binning_settings(device->physical_device); + struct radv_binning_settings *settings = &device->physical_device->binning_settings; const uint32_t pa_sc_binner_cntl_0 = S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) | S_028C44_BIN_SIZE_X(bin_size.width == 16) | S_028C44_BIN_SIZE_Y(bin_size.height == 16) | S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) | S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) | - S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) | - S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) | + S_028C44_CONTEXT_STATES_PER_BIN(settings->context_states_per_bin - 1) | + S_028C44_PERSISTENT_STATES_PER_BIN(settings->persistent_states_per_bin - 1) | S_028C44_DISABLE_START_OF_PRIM(1) | - S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1); + S_028C44_FPOVS_PER_BATCH(settings->fpovs_per_batch) | S_028C44_OPTIMAL_BIN_SELECTION(1); pipeline->binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0; } else diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index dc5c673..e74cc09 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -262,6 +262,12 @@ enum radv_queue_family { struct radv_perfcounter_desc; +struct radv_binning_settings { + unsigned context_states_per_bin; /* allowed range: [1, 6] */ + unsigned persistent_states_per_bin; /* allowed range: [1, 32] */ + unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */ +}; + struct radv_physical_device { struct vk_physical_device vk; @@ -339,6 +345,8 @@ struct radv_physical_device { struct ac_hs_info hs; struct ac_task_info task_info; + struct radv_binning_settings binning_settings; + /* Performance counters. */ struct ac_perfcounters ac_perfcounters; @@ -2174,14 +2182,6 @@ VkResult radv_compute_pipeline_create(VkDevice _device, VkPipelineCache _cache, void radv_pipeline_destroy(struct radv_device *device, struct radv_pipeline *pipeline, const VkAllocationCallbacks *allocator); -struct radv_binning_settings { - unsigned context_states_per_bin; /* allowed range: [1, 6] */ - unsigned persistent_states_per_bin; /* allowed range: [1, 32] */ - unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */ -}; - -struct radv_binning_settings radv_get_binning_settings(const struct radv_physical_device *pdev); - struct vk_format_description; uint32_t radv_translate_buffer_dataformat(const struct util_format_description *desc, int first_non_void); -- 2.7.4