From 3bc56086fc25f6d06ffc6d050cb6fc9724056aad Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 29 Apr 2015 11:26:51 +0900 Subject: [PATCH] local/mmc: dw_mmc: exynos: Change SAMPLE_CLK_TUNING bit This bit used bit[6:7]. We can assume the below values. 00 - 200ps 01 - 300ps 10 - 400ps 11 - 500ps This bit is set to maximum value(0x3) to use 500ps. Signed-off-by: Jaehoon Chung --- drivers/mmc/host/dw_mmc-exynos.c | 2 +- drivers/mmc/host/dw_mmc-exynos.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 6934b92..6b58432 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -442,7 +442,7 @@ static inline u8 dw_mci_exynos_move_next_clksmpl(struct dw_mci *host) sample = (clksel + 1) & 0x7; clksel = SDMMC_CLKSEL_UP_SAMPLE(clksel, sample) | - SDMMC_CLKSEL_SAMPLE_CLK_TUNING; + SDMMC_CLKSEL_SAMPLE_CLK_TUNING(0x3); if (priv->ctrl_type == DW_MCI_TYPE_EXYNOS7 || priv->ctrl_type == DW_MCI_TYPE_EXYNOS7_SMU) diff --git a/drivers/mmc/host/dw_mmc-exynos.h b/drivers/mmc/host/dw_mmc-exynos.h index c1f5d36..588ec16 100644 --- a/drivers/mmc/host/dw_mmc-exynos.h +++ b/drivers/mmc/host/dw_mmc-exynos.h @@ -34,7 +34,7 @@ SDMMC_CLKSEL_CCLK_DRIVE(y) | \ SDMMC_CLKSEL_CCLK_DIVIDER(z)) #define SDMMC_CLKSEL_TIMING_MASK SDMMC_CLKSEL_TIMING(0x7, 0x7, 0x7) -#define SDMMC_CLKSEL_SAMPLE_CLK_TUNING BIT(6) +#define SDMMC_CLKSEL_SAMPLE_CLK_TUNING(x) ((x) << 6) #define SDMMC_CLKSEL_WAKEUP_INT BIT(11) /* RCLK_EN register defines */ -- 2.7.4