From 3b33a28220344c98d8aa67fa6837857f31733916 Mon Sep 17 00:00:00 2001 From: Lei Zhang Date: Tue, 27 Mar 2012 16:19:44 +0800 Subject: [PATCH] Gfx-Display: correct the reg setting of MIPIA_PORT_CTRL in driver BZ: 29163 This patch corrects the reg setting of bit 23 in MIPIA_PORT_CTRL. This bit should be always set to 0 for PNWB0 and forward. The bit defination changed from PNW A0 to B0, but the Spec is not updated to the date. Here in driver correct this bit setting to 0 as required. Change-Id: I7bef71ccdeedd349a35259b78c1aab1fca0f3371 Signed-off-by: Lei Zhang Reviewed-on: http://android.intel.com:8080/40888 Reviewed-by: Xu, Randy Tested-by: Xu, Randy Reviewed-by: Ai, Ke Reviewed-by: buildbot Tested-by: buildbot --- drivers/staging/mrst/drv/mdfld_dsi_dpi.c | 23 +++++++++++++++++++---- drivers/staging/mrst/drv/psb_intel_dsi2.c | 10 ++++++++-- drivers/staging/mrst/drv/pyr_cmd.c | 2 +- drivers/staging/mrst/drv/tpo_cmd.c | 2 +- 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c index 3dce79d..ee4dfe9 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c @@ -320,7 +320,10 @@ void dsi_set_pipe_plane_enable_state(struct drm_device *dev, u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; - u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; + u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE; + + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mipi |= SEL_FLOPPED_HSTX; PSB_DEBUG_ENTRY("[DISPLAY TRK] %s: state = %d, pipe = %d\n", __func__, state, pipe); @@ -703,7 +706,10 @@ void dsi_set_pipe_plane_enable_state(struct drm_device *dev, int state, int pipe u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; - u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; + u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE; + + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mipi |= SEL_FLOPPED_HSTX; printk(KERN_ALERT "[DISPLAY TRK] %s: state = %d, pipe = %d\n", __func__, state, pipe); @@ -2214,7 +2220,13 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, u32 reg_offset = 0; u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; - u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; + u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE; + + /* The bit defination changed from PNW_A0 -> B0 and forward, + * Only for PNW_A0 that we need to set FLOPPED_HSTX + * */ + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mipi |= SEL_FLOPPED_HSTX; PSB_DEBUG_ENTRY("set mode %dx%d on pipe %d", mode->hdisplay, mode->vdisplay, pipe); @@ -2282,7 +2294,10 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, REG_WRITE(DEVICE_READY_REG, 0x00000001); /*0xB000 */ - REG_WRITE(mipi_reg, 0x80810000); /*0x61190 */ + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + REG_WRITE(mipi_reg, 0x80810000); /*0x61190 */ + else + REG_WRITE(mipi_reg, 0x80010000); /*0x61190 */ } #endif diff --git a/drivers/staging/mrst/drv/psb_intel_dsi2.c b/drivers/staging/mrst/drv/psb_intel_dsi2.c index 408c506..50b3034 100644 --- a/drivers/staging/mrst/drv/psb_intel_dsi2.c +++ b/drivers/staging/mrst/drv/psb_intel_dsi2.c @@ -2504,7 +2504,7 @@ static void mdfld_dpi_mode_set(struct drm_encoder *encoder, /* defaut to be dpi on values on pipe A. */ /* Enable MIPI Port */ - u32 mipi_val = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; + u32 mipi_val = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE; u32 mipi_control_val = 0x00000018; u32 dphy_param_val = 0x150c3408; /* dual dbi - dpi */ /* single = 0x0B14540C; */ u32 clk_lane_swt_val = 0x000A0014; @@ -2542,6 +2542,9 @@ static void mdfld_dpi_mode_set(struct drm_encoder *encoder, PSB_DEBUG_ENTRY("output_type = 0x%x \n", output->type); + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mipi_val |= SEL_FLOPPED_HSTX; + if (output->type == INTEL_OUTPUT_MIPI2) { /* MIPI_A has to be on before we can enable MIPI_C*/ @@ -2800,7 +2803,7 @@ static void mdfld_dbi_mode_set(struct drm_encoder *encoder, u32 disp_cntr_reg = DSPACNTR; /* defaut to be dbi values on pipe A. */ - u32 mipi_val = PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX; + u32 mipi_val = PASS_FROM_SPHY_TO_AFE; u32 dphy_param_val = 0x150c3408; /* dual dbi - dpi */ /* single 0x180a2b07; */ /*SLE 0x0b14540c;*/ /* HW SIMU 0x0b061a10; */ u32 mipi_control_val = 0x00000018; u32 hs_tx_timeout_val = 0x3fffff; @@ -2824,6 +2827,9 @@ static void mdfld_dbi_mode_set(struct drm_encoder *encoder, PSB_DEBUG_ENTRY("output_type = 0x%x \n", output->type); + if (dev_priv->platform_rev_id == MDFLD_PNW_A0) + mipi_val |= SEL_FLOPPED_HSTX; + if (output->type == INTEL_OUTPUT_MIPI2) { /* MIPI_A has to be on before we can enable MIPI_C*/ diff --git a/drivers/staging/mrst/drv/pyr_cmd.c b/drivers/staging/mrst/drv/pyr_cmd.c index eff7adb..a3799a6 100644 --- a/drivers/staging/mrst/drv/pyr_cmd.c +++ b/drivers/staging/mrst/drv/pyr_cmd.c @@ -267,7 +267,7 @@ static void pyr_dsi_dbi_mode_set(struct drm_encoder * encoder, u32 mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX); if (dev_priv->platform_rev_id != MDFLD_PNW_A0) - mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX | TE_TRIGGER_GPIO_PIN); + mipi_val = (PASS_FROM_SPHY_TO_AFE | TE_TRIGGER_GPIO_PIN); PSB_DEBUG_ENTRY("mipi_val =0x%x\n", mipi_val); diff --git a/drivers/staging/mrst/drv/tpo_cmd.c b/drivers/staging/mrst/drv/tpo_cmd.c index 684c0fd..1abb17e 100644 --- a/drivers/staging/mrst/drv/tpo_cmd.c +++ b/drivers/staging/mrst/drv/tpo_cmd.c @@ -238,7 +238,7 @@ static void mdfld_dsi_dbi_mode_set(struct drm_encoder * encoder, u32 mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX); if (dev_priv->platform_rev_id != MDFLD_PNW_A0) - mipi_val = (PASS_FROM_SPHY_TO_AFE | SEL_FLOPPED_HSTX | TE_TRIGGER_GPIO_PIN); + mipi_val = (PASS_FROM_SPHY_TO_AFE | TE_TRIGGER_GPIO_PIN); PSB_DEBUG_ENTRY("mipi_val =0x%x\n", mipi_val); -- 2.7.4