From 3b132300728e7ed06e59e449ceb8175305869a49 Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov@redhat.com>
Date: Thu, 21 Apr 2022 10:06:47 +0200
Subject: [PATCH] [GVNSink] Regenerate test checks (NFC)

---
 llvm/test/Transforms/GVNSink/sink-common-code.ll | 524 ++++++++++++++++-------
 1 file changed, 375 insertions(+), 149 deletions(-)

diff --git a/llvm/test/Transforms/GVNSink/sink-common-code.ll b/llvm/test/Transforms/GVNSink/sink-common-code.ll
index d0b533b..472e0cb 100644
--- a/llvm/test/Transforms/GVNSink/sink-common-code.ll
+++ b/llvm/test/Transforms/GVNSink/sink-common-code.ll
@@ -1,14 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -gvn-sink -simplifycfg -simplifycfg-require-and-preserve-domtree=1 -hoist-common-insts=true -simplifycfg-sink-common=false -S | FileCheck %s
 
 define zeroext i1 @test1(i1 zeroext %flag, i32 %blksA, i32 %blksB, i32 %nblks) {
+; CHECK-LABEL: @test1(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[BLKSA:%.*]], [[NBLKS:%.*]]
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[NBLKS]], [[BLKSB:%.*]]
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[ADD]], [[BLKSA]]
+; CHECK-NEXT:    [[CMP_SINK:%.*]] = select i1 [[FLAG:%.*]], i1 [[CMP]], i1 [[CMP2]]
+; CHECK-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[CMP_SINK]] to i8
+; CHECK-NEXT:    [[TOBOOL4:%.*]] = icmp ne i8 [[FROMBOOL1]], 0
+; CHECK-NEXT:    ret i1 [[TOBOOL4]]
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
-; CHECK-LABEL: test1
-; CHECK: add
-; CHECK: select
-; CHECK: icmp
-; CHECK-NOT: br
 if.then:
   %cmp = icmp uge i32 %blksA, %nblks
   %frombool1 = zext i1 %cmp to i8
@@ -27,14 +33,18 @@ if.end:
 }
 
 define zeroext i1 @test2(i1 zeroext %flag, i32 %blksA, i32 %blksB, i32 %nblks) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[NBLKS:%.*]], [[BLKSB:%.*]]
+; CHECK-NEXT:    [[NBLKS_SINK:%.*]] = select i1 [[FLAG:%.*]], i32 [[NBLKS]], i32 [[ADD]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[BLKSA:%.*]], [[NBLKS_SINK]]
+; CHECK-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[CMP]] to i8
+; CHECK-NEXT:    [[TOBOOL4:%.*]] = icmp ne i8 [[FROMBOOL1]], 0
+; CHECK-NEXT:    ret i1 [[TOBOOL4]]
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
-; CHECK-LABEL: test2
-; CHECK: add
-; CHECK: select
-; CHECK: icmp
-; CHECK-NOT: br
 if.then:
   %cmp = icmp uge i32 %blksA, %nblks
   %frombool1 = zext i1 %cmp to i8
@@ -86,6 +96,13 @@ declare i32 @foo(i32, i32) nounwind readnone
 ; -CHECK-NOT: br
 
 define i32 @test4(i1 zeroext %flag, i32 %x, i32* %y) {
+; CHECK-LABEL: @test4(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[FLAG:%.*]], i32 5, i32 7
+; CHECK-NEXT:    [[A:%.*]] = add i32 [[X:%.*]], [[DOT]]
+; CHECK-NEXT:    store i32 [[A]], i32* [[Y:%.*]], align 4
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -103,12 +120,21 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test4
-; CHECK: select
-; CHECK: store
-; CHECK-NOT: store
-
 define i32 @test5(i1 zeroext %flag, i32 %x, i32* %y) {
+; CHECK-LABEL: @test5(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[A:%.*]] = add i32 [[X:%.*]], 5
+; CHECK-NEXT:    store volatile i32 [[A]], i32* [[Y:%.*]], align 4
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[B:%.*]] = add i32 [[X]], 7
+; CHECK-NEXT:    store i32 [[B]], i32* [[Y]], align 4
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -126,11 +152,14 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test5
-; CHECK: store volatile
-; CHECK: store
-
 define i32 @test6(i1 zeroext %flag, i32 %x, i32* %y) {
+; CHECK-LABEL: @test6(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[FLAG:%.*]], i32 5, i32 7
+; CHECK-NEXT:    [[A:%.*]] = add i32 [[X:%.*]], [[DOT]]
+; CHECK-NEXT:    store volatile i32 [[A]], i32* [[Y:%.*]], align 4
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -148,12 +177,15 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test6
-; CHECK: select
-; CHECK: store volatile
-; CHECK-NOT: store
-
 define i32 @test7(i1 zeroext %flag, i32 %x, i32* %y) {
+; CHECK-LABEL: @test7(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[FLAG:%.*]], i32 5, i32 7
+; CHECK-NEXT:    [[Z:%.*]] = load volatile i32, i32* [[Y:%.*]], align 4
+; CHECK-NEXT:    [[A:%.*]] = add i32 [[Z]], [[DOT]]
+; CHECK-NEXT:    store volatile i32 [[A]], i32* [[Y]], align 4
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -173,15 +205,26 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test7
-; CHECK-DAG: select
-; CHECK-DAG: load volatile
-; CHECK: store volatile
-; CHECK-NOT: load
-; CHECK-NOT: store
-
 ; The extra store in %if.then means %z and %w are not equivalent.
 define i32 @test9(i1 zeroext %flag, i32 %x, i32* %y, i32* %p) {
+; CHECK-LABEL: @test9(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    store i32 7, i32* [[P:%.*]], align 4
+; CHECK-NEXT:    [[Z:%.*]] = load volatile i32, i32* [[Y:%.*]], align 4
+; CHECK-NEXT:    store i32 6, i32* [[P]], align 4
+; CHECK-NEXT:    [[A:%.*]] = add i32 [[Z]], 5
+; CHECK-NEXT:    store volatile i32 [[A]], i32* [[Y]], align 4
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[W:%.*]] = load volatile i32, i32* [[Y]], align 4
+; CHECK-NEXT:    [[B:%.*]] = add i32 [[W]], 7
+; CHECK-NEXT:    store volatile i32 [[B]], i32* [[Y]], align 4
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -203,14 +246,26 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test9
-; CHECK: add
-; CHECK: add
-
 %struct.anon = type { i32, i32 }
 
 ; The GEP indexes a struct type so cannot have a variable last index.
 define i32 @test10(i1 zeroext %flag, i32 %x, i32* %y, %struct.anon* %s) {
+; CHECK-LABEL: @test10(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[DUMMY:%.*]] = add i32 [[X:%.*]], 5
+; CHECK-NEXT:    [[GEPA:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[S:%.*]], i32 0, i32 0
+; CHECK-NEXT:    store volatile i32 [[X]], i32* [[GEPA]], align 4
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[DUMMY1:%.*]] = add i32 [[X]], 6
+; CHECK-NEXT:    [[GEPB:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[S]], i32 0, i32 1
+; CHECK-NEXT:    store volatile i32 [[X]], i32* [[GEPB]], align 4
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -230,14 +285,23 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test10
-; CHECK: getelementptr
-; CHECK: store volatile
-; CHECK: getelementptr
-; CHECK: store volatile
-
 ; The shufflevector's mask operand cannot be merged in a PHI.
 define i32 @test11(i1 zeroext %flag, i32 %w, <2 x i32> %x, <2 x i32> %y) {
+; CHECK-LABEL: @test11(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[DUMMY:%.*]] = add i32 [[W:%.*]], 5
+; CHECK-NEXT:    [[SV1:%.*]] = shufflevector <2 x i32> [[X:%.*]], <2 x i32> [[Y:%.*]], <2 x i32> <i32 0, i32 1>
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[DUMMY1:%.*]] = add i32 [[W]], 6
+; CHECK-NEXT:    [[SV2:%.*]] = shufflevector <2 x i32> [[X]], <2 x i32> [[Y]], <2 x i32> <i32 1, i32 0>
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[P:%.*]] = phi <2 x i32> [ [[SV1]], [[IF_THEN]] ], [ [[SV2]], [[IF_ELSE]] ]
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -256,12 +320,23 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test11
-; CHECK: shufflevector
-; CHECK: shufflevector
-
 ; We can't common an intrinsic!
 define i32 @test12(i1 zeroext %flag, i32 %w, i32 %x, i32 %y) {
+; CHECK-LABEL: @test12(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[DUMMY:%.*]] = add i32 [[W:%.*]], 5
+; CHECK-NEXT:    [[SV1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false)
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[DUMMY1:%.*]] = add i32 [[W]], 6
+; CHECK-NEXT:    [[SV2:%.*]] = call i32 @llvm.cttz.i32(i32 [[X]], i1 false)
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ [[SV1]], [[IF_THEN]] ], [ [[SV2]], [[IF_ELSE]] ]
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -283,12 +358,16 @@ if.end:
 declare i32 @llvm.ctlz.i32(i32 %x) readnone
 declare i32 @llvm.cttz.i32(i32 %x) readnone
 
-; CHECK-LABEL: test12
-; CHECK: call i32 @llvm.ctlz
-; CHECK: call i32 @llvm.cttz
-
 ; The TBAA metadata should be properly combined.
 define i32 @test13(i1 zeroext %flag, i32 %x, i32* %y) {
+; CHECK-LABEL: @test13(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[FLAG:%.*]], i32 5, i32 7
+; CHECK-NEXT:    [[Z:%.*]] = load volatile i32, i32* [[Y:%.*]], align 4
+; CHECK-NEXT:    [[A:%.*]] = add i32 [[Z]], [[DOT]]
+; CHECK-NEXT:    store volatile i32 [[A]], i32* [[Y]], align 4, !tbaa [[TBAA0:![0-9]+]]
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -314,15 +393,14 @@ if.end:
 !3 = !{ !"const float", !2, i64 0 }
 !4 = !{ !"special float", !2, i64 1 }
 
-; CHECK-LABEL: test13
-; CHECK-DAG: select
-; CHECK-DAG: load volatile
-; CHECK: store volatile {{.*}}, !tbaa !0
-; CHECK-NOT: load
-; CHECK-NOT: store
-
 ; The call should be commoned.
 define i32 @test13a(i1 zeroext %flag, i32 %w, i32 %x, i32 %y) {
+; CHECK-LABEL: @test13a(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[X_Y:%.*]] = select i1 [[FLAG:%.*]], i32 [[X:%.*]], i32 [[Y:%.*]]
+; CHECK-NEXT:    [[SV1:%.*]] = call i32 @bar(i32 [[X_Y]])
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -340,12 +418,24 @@ if.end:
 }
 declare i32 @bar(i32)
 
-; CHECK-LABEL: test13a
-; CHECK: %[[x:.*]] = select i1 %flag
-; CHECK: call i32 @bar(i32 %[[x]])
-
 ; The load should be commoned.
 define i32 @test14(i1 zeroext %flag, i32 %w, i32 %x, i32 %y, %struct.anon* %s) {
+; CHECK-LABEL: @test14(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[DUMMY:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[DUMMY2:%.*]] = add i32 [[X]], 4
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[DOTSINK:%.*]] = phi i32 [ 56, [[IF_THEN]] ], [ 57, [[IF_ELSE]] ]
+; CHECK-NEXT:    [[GEPA:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[S:%.*]], i32 0, i32 1
+; CHECK-NEXT:    [[SV1:%.*]] = load i32, i32* [[GEPA]], align 4
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[SV1]], [[DOTSINK]]
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -368,13 +458,26 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test14
-; CHECK: getelementptr
-; CHECK: load
-; CHECK-NOT: load
-
 ; The load should be commoned.
 define i32 @test15(i1 zeroext %flag, i32 %w, i32 %x, i32 %y, %struct.anon* %s) {
+; CHECK-LABEL: @test15(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[DUMMY:%.*]] = add i32 [[X:%.*]], 1
+; CHECK-NEXT:    [[GEPA:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[S:%.*]], i32 0, i32 0
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[DUMMY2:%.*]] = add i32 [[X]], 4
+; CHECK-NEXT:    [[GEPB:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[S]], i32 0, i32 1
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[GEPA_SINK:%.*]] = phi i32* [ [[GEPA]], [[IF_THEN]] ], [ [[GEPB]], [[IF_ELSE]] ]
+; CHECK-NEXT:    [[SV1:%.*]] = load i32, i32* [[GEPA_SINK]], align 4
+; CHECK-NEXT:    [[EXT1:%.*]] = zext i32 [[SV1]] to i64
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i64 [[EXT1]], 56
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -399,12 +502,24 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: test15
-; CHECK: getelementptr
-; CHECK: load
-; CHECK-NOT: load
-
 define zeroext i1 @test_crash(i1 zeroext %flag, i32* %i4, i32* %m, i32* %n) {
+; CHECK-LABEL: @test_crash(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[TMP1:%.*]] = load i32, i32* [[I4:%.*]], align 4
+; CHECK-NEXT:    [[TMP2:%.*]] = add i32 [[TMP1]], -1
+; CHECK-NEXT:    store i32 [[TMP2]], i32* [[I4]], align 4
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[TMP3:%.*]] = load i32, i32* [[M:%.*]], align 4
+; CHECK-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N:%.*]], align 4
+; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[TMP3]], [[TMP4]]
+; CHECK-NEXT:    store i32 [[TMP5]], i32* [[I4]], align 4
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i1 true
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -425,11 +540,26 @@ if.end:
   ret i1 true
 }
 
-; CHECK-LABEL: test_crash
-; No checks for test_crash - just ensure it doesn't crash!
-
 define zeroext i1 @test16(i1 zeroext %flag, i1 zeroext %flag2, i32 %blksA, i32 %blksB, i32 %nblks) {
-
+; CHECK-LABEL: @test16(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[BLKSA:%.*]], [[NBLKS:%.*]]
+; CHECK-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[CMP]] to i8
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    br i1 [[FLAG2:%.*]], label [[IF_THEN2:%.*]], label [[IF_END]]
+; CHECK:       if.then2:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[NBLKS]], [[BLKSB:%.*]]
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[ADD]], [[BLKSA]]
+; CHECK-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[CMP2]] to i8
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[OBEYS_0:%.*]] = phi i8 [ [[FROMBOOL1]], [[IF_THEN]] ], [ [[FROMBOOL3]], [[IF_THEN2]] ], [ 0, [[IF_ELSE]] ]
+; CHECK-NEXT:    [[TOBOOL4:%.*]] = icmp ne i8 [[OBEYS_0]], 0
+; CHECK-NEXT:    ret i1 [[TOBOOL4]]
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -453,12 +583,29 @@ if.end:
   ret i1 %tobool4
 }
 
-; CHECK-LABEL: test16
-; CHECK: zext
-; CHECK: zext
-
 define zeroext i1 @test16a(i1 zeroext %flag, i1 zeroext %flag2, i32 %blksA, i32 %blksB, i32 %nblks, i8* %p) {
-
+; CHECK-LABEL: @test16a(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[BLKSA:%.*]], [[NBLKS:%.*]]
+; CHECK-NEXT:    br label [[IF_END_GVNSINK_SPLIT:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    br i1 [[FLAG2:%.*]], label [[IF_THEN2:%.*]], label [[IF_END:%.*]]
+; CHECK:       if.then2:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[NBLKS]], [[BLKSB:%.*]]
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[ADD]], [[BLKSA]]
+; CHECK-NEXT:    br label [[IF_END_GVNSINK_SPLIT]]
+; CHECK:       if.end.gvnsink.split:
+; CHECK-NEXT:    [[CMP_SINK:%.*]] = phi i1 [ [[CMP]], [[IF_THEN]] ], [ [[CMP2]], [[IF_THEN2]] ]
+; CHECK-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[CMP_SINK]] to i8
+; CHECK-NEXT:    [[B1:%.*]] = sext i8 [[FROMBOOL1]] to i32
+; CHECK-NEXT:    [[B2:%.*]] = trunc i32 [[B1]] to i8
+; CHECK-NEXT:    store i8 [[B2]], i8* [[P:%.*]], align 1
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i1 true
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -486,15 +633,38 @@ if.end:
   ret i1 true
 }
 
-; CHECK-LABEL: test16a
-; CHECK: zext
-; CHECK-NOT: zext
-
+; FIXME: we don't consider this profitable. We should
+;  - Consider argument setup/return mov'ing for calls, like InlineCost does.
+;  - Consider the removal of the %obeys.0 PHI (zero PHI movement overall)
 define zeroext i1 @test17(i32 %flag, i32 %blksA, i32 %blksB, i32 %nblks) {
+; CHECK-LABEL: @test17(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[FLAG:%.*]], label [[IF_END:%.*]] [
+; CHECK-NEXT:    i32 0, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[BLKSA:%.*]], [[NBLKS:%.*]]
+; CHECK-NEXT:    [[FROMBOOL1:%.*]] = call i8 @i1toi8(i1 [[CMP]])
+; CHECK-NEXT:    [[A1:%.*]] = sext i8 [[FROMBOOL1]] to i32
+; CHECK-NEXT:    [[A2:%.*]] = trunc i32 [[A1]] to i8
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.then2:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[NBLKS]], [[BLKSB:%.*]]
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[ADD]], [[BLKSA]]
+; CHECK-NEXT:    [[FROMBOOL3:%.*]] = call i8 @i1toi8(i1 [[CMP2]])
+; CHECK-NEXT:    [[B1:%.*]] = sext i8 [[FROMBOOL3]] to i32
+; CHECK-NEXT:    [[B2:%.*]] = trunc i32 [[B1]] to i8
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[OBEYS_0:%.*]] = phi i8 [ [[A2]], [[IF_THEN]] ], [ [[B2]], [[IF_THEN2]] ], [ 0, [[ENTRY:%.*]] ]
+; CHECK-NEXT:    [[TOBOOL4:%.*]] = icmp ne i8 [[OBEYS_0]], 0
+; CHECK-NEXT:    ret i1 [[TOBOOL4]]
+;
 entry:
   switch i32 %flag, label %if.end [
-    i32 0, label %if.then
-    i32 1, label %if.then2
+  i32 0, label %if.then
+  i32 1, label %if.then2
   ]
 
 if.then:
@@ -519,35 +689,34 @@ if.end:
 }
 declare i8 @i1toi8(i1)
 
-; FIXME: DISABLED - we don't consider this profitable. We should
-;  - Consider argument setup/return mov'ing for calls, like InlineCost does.
-;  - Consider the removal of the %obeys.0 PHI (zero PHI movement overall)
-
-; DISABLED-CHECK-LABEL: test17
-; DISABLED-CHECK: if.then:
-; DISABLED-CHECK-NEXT: icmp uge
-; DISABLED-CHECK-NEXT: br label %[[x:.*]]
-
-; DISABLED-CHECK: if.then2:
-; DISABLED-CHECK-NEXT: add
-; DISABLED-CHECK-NEXT: icmp ule
-; DISABLED-CHECK-NEXT: br label %[[x]]
-
-; DISABLED-CHECK: [[x]]:
-; DISABLED-CHECK-NEXT: %[[y:.*]] = phi i1 [ %cmp
-; DISABLED-CHECK-NEXT: %[[z:.*]] = call i8 @i1toi8(i1 %[[y]])
-; DISABLED-CHECK-NEXT: br label %if.end
-
-; DISABLED-CHECK: if.end:
-; DISABLED-CHECK-NEXT: phi i8
-; DISABLED-CHECK-DAG: [ %[[z]], %[[x]] ]
-; DISABLED-CHECK-DAG: [ 0, %entry ]
-
 define zeroext i1 @test18(i32 %flag, i32 %blksA, i32 %blksB, i32 %nblks) {
+; CHECK-LABEL: @test18(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    switch i32 [[FLAG:%.*]], label [[IF_THEN3:%.*]] [
+; CHECK-NEXT:    i32 0, label [[IF_THEN:%.*]]
+; CHECK-NEXT:    i32 1, label [[IF_THEN2:%.*]]
+; CHECK-NEXT:    ]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[BLKSA:%.*]], [[NBLKS:%.*]]
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.then2:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[NBLKS]], [[BLKSB:%.*]]
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[ADD]], [[BLKSA]]
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.then3:
+; CHECK-NEXT:    [[ADD2:%.*]] = add i32 [[NBLKS]], [[BLKSA]]
+; CHECK-NEXT:    [[CMP3:%.*]] = icmp ule i32 [[ADD2]], [[BLKSA]]
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[CMP3_SINK:%.*]] = phi i1 [ [[CMP3]], [[IF_THEN3]] ], [ [[CMP]], [[IF_THEN]] ], [ [[CMP2]], [[IF_THEN2]] ]
+; CHECK-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3_SINK]] to i8
+; CHECK-NEXT:    [[TOBOOL4:%.*]] = icmp ne i8 [[FROMBOOL4]], 0
+; CHECK-NEXT:    ret i1 [[TOBOOL4]]
+;
 entry:
   switch i32 %flag, label %if.then3 [
-    i32 0, label %if.then
-    i32 1, label %if.then2
+  i32 0, label %if.then
+  i32 1, label %if.then2
   ]
 
 if.then:
@@ -573,18 +742,22 @@ if.end:
   ret i1 %tobool4
 }
 
-; CHECK-LABEL: test18
-; CHECK: if.end:
-; CHECK-NEXT: %[[x:.*]] = phi i1
-; CHECK-DAG: [ %cmp, %if.then ]
-; CHECK-DAG: [ %cmp2, %if.then2 ]
-; CHECK-DAG: [ %cmp3, %if.then3 ]
-; CHECK-NEXT: zext i1 %[[x]] to i8
-
 ; The phi is confusing - both add instructions are used by it, but
 ; not on their respective unconditional arcs. It should not be
 ; optimized.
 define void @test_pr30292(i1 %cond, i1 %cond2, i32 %a, i32 %b) {
+; CHECK-LABEL: @test_pr30292(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[ADD1:%.*]] = add i32 [[A:%.*]], 1
+; CHECK-NEXT:    br label [[SUCC:%.*]]
+; CHECK:       two:
+; CHECK-NEXT:    call void @g()
+; CHECK-NEXT:    [[ADD2:%.*]] = add i32 [[A]], 1
+; CHECK-NEXT:    br label [[SUCC]]
+; CHECK:       succ:
+; CHECK-NEXT:    [[P:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD1]], [[SUCC]] ], [ [[ADD2]], [[TWO:%.*]] ]
+; CHECK-NEXT:    br i1 [[COND:%.*]], label [[TWO]], label [[SUCC]]
+;
 entry:
   %add1 = add i32 %a, 1
   br label %succ
@@ -603,11 +776,28 @@ succ:
 }
 declare void @g()
 
-; CHECK-LABEL: test_pr30292
-; CHECK: phi i32 [ 0, %entry ], [ %add1, %succ ], [ %add2, %two ]
-
 define zeroext i1 @test_pr30244(i1 zeroext %flag, i1 zeroext %flag2, i32 %blksA, i32 %blksB, i32 %nblks) {
-
+; CHECK-LABEL: @test_pr30244(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[P:%.*]] = alloca i8, align 1
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[CMP:%.*]] = icmp uge i32 [[BLKSA:%.*]], [[NBLKS:%.*]]
+; CHECK-NEXT:    br label [[IF_END_GVNSINK_SPLIT:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    br i1 [[FLAG2:%.*]], label [[IF_THEN2:%.*]], label [[IF_END:%.*]]
+; CHECK:       if.then2:
+; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[NBLKS]], [[BLKSB:%.*]]
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ule i32 [[ADD]], [[BLKSA]]
+; CHECK-NEXT:    br label [[IF_END_GVNSINK_SPLIT]]
+; CHECK:       if.end.gvnsink.split:
+; CHECK-NEXT:    [[CMP_SINK:%.*]] = phi i1 [ [[CMP]], [[IF_THEN]] ], [ [[CMP2]], [[IF_THEN2]] ]
+; CHECK-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[CMP_SINK]] to i8
+; CHECK-NEXT:    store i8 [[FROMBOOL1]], i8* [[P]], align 1
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i1 true
+;
 entry:
   %p = alloca i8
   br i1 %flag, label %if.then, label %if.else
@@ -632,11 +822,24 @@ if.end:
   ret i1 true
 }
 
-; CHECK-LABEL: @test_pr30244
-; CHECK: store
-; CHECK-NOT: store
-
 define i32 @test_pr30373a(i1 zeroext %flag, i32 %x, i32 %y) {
+; CHECK-LABEL: @test_pr30373a(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[X0:%.*]] = call i32 @foo(i32 [[X:%.*]], i32 0) #[[ATTR0:[0-9]+]]
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[X1:%.*]] = call i32 @foo(i32 [[Y:%.*]], i32 0) #[[ATTR0]]
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[X_SINK:%.*]] = phi i32 [ [[X]], [[IF_THEN]] ], [ [[Y]], [[IF_ELSE]] ]
+; CHECK-NEXT:    [[XX:%.*]] = phi i32 [ [[X0]], [[IF_THEN]] ], [ [[X1]], [[IF_ELSE]] ]
+; CHECK-NEXT:    [[Y0:%.*]] = call i32 @foo(i32 [[X_SINK]], i32 1) #[[ATTR0]]
+; CHECK-NEXT:    [[Z0:%.*]] = lshr i32 [[Y0]], 8
+; CHECK-NEXT:    [[RET:%.*]] = add i32 [[XX]], [[Z0]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -659,12 +862,24 @@ if.end:
   ret i32 %ret
 }
 
-; CHECK-LABEL: test_pr30373a
-; CHECK: lshr
-; CHECK-NOT: exact
-; CHECK: }
-
 define i32 @test_pr30373b(i1 zeroext %flag, i32 %x, i32 %y) {
+; CHECK-LABEL: @test_pr30373b(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[X0:%.*]] = call i32 @foo(i32 [[X:%.*]], i32 0) #[[ATTR0]]
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[X1:%.*]] = call i32 @foo(i32 [[Y:%.*]], i32 0) #[[ATTR0]]
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    [[X_SINK:%.*]] = phi i32 [ [[X]], [[IF_THEN]] ], [ [[Y]], [[IF_ELSE]] ]
+; CHECK-NEXT:    [[XX:%.*]] = phi i32 [ [[X0]], [[IF_THEN]] ], [ [[X1]], [[IF_ELSE]] ]
+; CHECK-NEXT:    [[Y0:%.*]] = call i32 @foo(i32 [[X_SINK]], i32 1) #[[ATTR0]]
+; CHECK-NEXT:    [[Z0:%.*]] = lshr i32 [[Y0]], 8
+; CHECK-NEXT:    [[RET:%.*]] = add i32 [[XX]], [[Z0]]
+; CHECK-NEXT:    ret i32 [[RET]]
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -687,17 +902,14 @@ if.end:
   ret i32 %ret
 }
 
-; CHECK-LABEL: test_pr30373b
-; CHECK: lshr
-; CHECK-NOT: exact
-; CHECK: }
-
-
-; CHECK-LABEL: @common_bitcast(
-; CHECK: %. = select i1 %flag, float 2.000000e+00, float 1.000000e+00
-; CHECK: %[[a1:.*]] = bitcast i32* %x to float*
-; CHECK: store float %., float* %[[a1]]
 define i32 @common_bitcast(i1 zeroext %flag, i32* %x) {
+; CHECK-LABEL: @common_bitcast(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[FLAG:%.*]], float 2.000000e+00, float 1.000000e+00
+; CHECK-NEXT:    [[A:%.*]] = bitcast i32* [[X:%.*]] to float*
+; CHECK-NEXT:    store float [[DOT]], float* [[A]], align 4
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -715,11 +927,14 @@ if.end:
   ret i32 1
 }
 
-; CHECK-LABEL: @common_addrspacecast(
-; CHECK: %. = select i1 %flag, i32 9, i32 10
-; CHECK: %[[a2:.*]] = addrspacecast i32* %x to i32 addrspace(1)*
-; CHECK: store i32 %., i32 addrspace(1)* %[[a2]]
 define i32 @common_addrspacecast(i1 zeroext %flag, i32* %x) {
+; CHECK-LABEL: @common_addrspacecast(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[DOT:%.*]] = select i1 [[FLAG:%.*]], i32 9, i32 10
+; CHECK-NEXT:    [[A:%.*]] = addrspacecast i32* [[X:%.*]] to i32 addrspace(1)*
+; CHECK-NEXT:    store i32 [[DOT]], i32 addrspace(1)* [[A]], align 4
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
@@ -738,10 +953,21 @@ if.end:
 }
 
 ; Don't merge different address spaces
-; CHECK-LABEL: @no_common_addrspacecast(
-; CHECK: addrspacecast i32* %x to i32 addrspace(1)*
-; CHECK: addrspacecast i32* %x to i32 addrspace(3)*
 define i32 @no_common_addrspacecast(i1 zeroext %flag, i32* %x) {
+; CHECK-LABEL: @no_common_addrspacecast(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    br i1 [[FLAG:%.*]], label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]]
+; CHECK:       if.then:
+; CHECK-NEXT:    [[A:%.*]] = addrspacecast i32* [[X:%.*]] to i32 addrspace(1)*
+; CHECK-NEXT:    store i32 9, i32 addrspace(1)* [[A]], align 4
+; CHECK-NEXT:    br label [[IF_END:%.*]]
+; CHECK:       if.else:
+; CHECK-NEXT:    [[B:%.*]] = addrspacecast i32* [[X]] to i32 addrspace(3)*
+; CHECK-NEXT:    store i32 10, i32 addrspace(3)* [[B]], align 4
+; CHECK-NEXT:    br label [[IF_END]]
+; CHECK:       if.end:
+; CHECK-NEXT:    ret i32 1
+;
 entry:
   br i1 %flag, label %if.then, label %if.else
 
-- 
2.7.4