From 3ab7f4471c933767dff79638e79739323d938177 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 27 Jan 2022 10:26:58 +0200 Subject: [PATCH] isl: disable CPB surface compression Signed-off-by: Lionel Landwerlin Reviewed-by: Nanley Chery Part-of: --- src/intel/isl/isl.c | 6 ++++++ src/intel/isl/isl_emit_cpb.c | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index e16661d..bd41684 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -2161,6 +2161,12 @@ isl_surf_supports_ccs(const struct isl_device *dev, if (surf->tiling == ISL_TILING_LINEAR) return false; + /* TODO: Disable for now, as we're not sure about the meaning of + * 3DSTATE_CPSIZE_CONTROL_BUFFER::CPCBCompressionEnable + */ + if (isl_surf_usage_is_cpb(surf->usage)) + return false; + if (ISL_GFX_VER(dev) >= 12) { if (isl_surf_usage_is_stencil(surf->usage)) { /* HiZ and MCS aren't allowed with stencil */ diff --git a/src/intel/isl/isl_emit_cpb.c b/src/intel/isl/isl_emit_cpb.c index 024fba9..eeb3337 100644 --- a/src/intel/isl/isl_emit_cpb.c +++ b/src/intel/isl/isl_emit_cpb.c @@ -96,6 +96,11 @@ isl_genX(emit_cpb_control_s)(const struct isl_device *dev, void *batch, * Start LOD" to 15 to prevent the hardware from trying to use them. */ cpb.MipTailStartLOD = 15; + /* TODO: + * + * cpb.CPCBCompressionEnable is this CCS compression? Currently disabled + * in isl_surf_supports_ccs() for CPB buffers. + */ } else { cpb.SurfaceType = SURFTYPE_NULL; cpb.TiledMode = TILE64; -- 2.7.4