From 3a9f6bb21d083640c5770fa663c4ce806fd853a5 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 18 Jun 2020 16:16:51 +0800 Subject: [PATCH] drm/amd/pm: correct the BootLinkLevel setup Set the BootLinkLevel as the max level. Signed-off-by: Evan Quan Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c index a6c8f12..d9d53fb 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c +++ b/drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c @@ -2023,7 +2023,7 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) table->VoltageResponseTime = 0; table->PhaseResponseTime = 0; table->MemoryThermThrottleEnable = 1; - table->PCIeBootLinkLevel = 0; + table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count; table->PCIeGenInterval = 1; table->VRConfig = 0; -- 2.7.4