From 3a6ee9f4e68c4087c33a44154a106737aaaf0e7a Mon Sep 17 00:00:00 2001 From: Michael Meissner Date: Fri, 16 Mar 2001 18:10:12 +0000 Subject: [PATCH] Fix some MIPS warnings From-SVN: r40556 --- gcc/ChangeLog | 23 +++++++++++++++++++++++ gcc/config/mips/mips.c | 17 ++++++++++------- gcc/config/mips/mips.h | 7 +++++++ gcc/config/mips/mips.md | 24 ++++++++++++------------ 4 files changed, 52 insertions(+), 19 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 27699c8..72ee628 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2001-03-16 Michael Meissner + + * mips.h (BITMASK_HIGH): Replacement for 0x80000000 that avoids + warnings. + (BITMASK_UPPER16): Replacement for 0xffff0000 that avoids + warnings. + (BITMASK_LOWER16): Replacement for 0x0000ffff. + + * mips.c (save_restore_insns): Use BITMASK_UPPER16/BITMASK_LOWER16 + instead of 0xffff0000/0x0000ffff to avoid warnings about constants + being unsigned in ISO C and signed in traditional. + (expand_prologue): Ditto. + (RA_MASK): Use BITMASK_HIGH to avoid warnings. + + * mips.md (divmodsi4,divmodsi4): Use BITMASK_HIGH to avoid + warnings. + (divsi3,divdi3): Ditto. + (modsi3,moddi3): Ditto. + (fix_truncdfsi2,fix_truncdfdi2): Ditto. + (fix_truncsfsi2,fix_truncsfdi2): Ditto. + (movsi split): Use BITMASK_UPPER16/BITMASK_LOWER16 to avoid + warnings. + Fri Mar 16 14:47:57 CET 2001 Jan Hubicka * i386.c (ix86_expand_fp_movcc): Do not attempt to construct diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 8467c88..23a05bc 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -6452,12 +6452,13 @@ save_restore_insns (store_p, large_reg, large_offset, file) && GET_MODE (base_reg_rtx) == SImode) { insn = emit_move_insn (base_reg_rtx, - GEN_INT (gp_offset & 0xffff0000)); + GEN_INT (gp_offset & BITMASK_UPPER16)); if (store_p) RTX_FRAME_RELATED_P (insn) = 1; insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, - GEN_INT (gp_offset & 0x0000ffff))); + GEN_INT (gp_offset + & BITMASK_LOWER16))); if (store_p) RTX_FRAME_RELATED_P (insn) = 1; } @@ -6671,11 +6672,12 @@ save_restore_insns (store_p, large_reg, large_offset, file) && GET_MODE (base_reg_rtx) == SImode) { insn = emit_move_insn (base_reg_rtx, - GEN_INT (fp_offset & 0xffff0000)); + GEN_INT (fp_offset & BITMASK_UPPER16)); if (store_p) RTX_FRAME_RELATED_P (insn) = 1; insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx, - GEN_INT (fp_offset & 0x0000ffff))); + GEN_INT (fp_offset + & BITMASK_LOWER16))); if (store_p) RTX_FRAME_RELATED_P (insn) = 1; } @@ -7223,10 +7225,11 @@ mips_expand_prologue () && GET_MODE (tmp_rtx) == SImode) { insn = emit_move_insn (tmp_rtx, - GEN_INT (tsize & 0xffff0000)); + GEN_INT (tsize & BITMASK_UPPER16)); RTX_FRAME_RELATED_P (insn) = 1; insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx, - GEN_INT (tsize & 0x0000ffff))); + GEN_INT (tsize + & BITMASK_LOWER16))); RTX_FRAME_RELATED_P (insn) = 1; } else @@ -7342,7 +7345,7 @@ mips_expand_prologue () /* Do any necessary cleanup after a function to restore stack, frame, and regs. */ -#define RA_MASK 0x80000000L /* 1 << 31 */ +#define RA_MASK BITMASK_HIGH /* 1 << 31 */ #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST)) void diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 1510ecc..cdd0009 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -179,6 +179,13 @@ extern void sbss_section PARAMS ((void)); #define HALF_PIC_FINISH(STREAM) #endif +/* Macros to silence warnings about numbers being signed in traditional + C and unsigned in ISO C when compiled on 32-bit hosts. */ + +#define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */ +#define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */ +#define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */ + /* Run-time compilation parameters selecting different hardware subsets. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 1f343f5..ceb4f6a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -2277,7 +2277,7 @@ copy_to_mode_reg (SImode, GEN_INT (-1)), GEN_INT (0x6))); emit_insn (gen_div_trap (operands[2], - copy_to_mode_reg (SImode, GEN_INT (0x80000000)), + copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } @@ -2324,7 +2324,7 @@ copy_to_mode_reg (DImode, GEN_INT (-1)), GEN_INT (0x6))); emit_insn (gen_div_trap (operands[2], - copy_to_mode_reg (DImode, GEN_INT (0x80000000)), + copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } @@ -2535,7 +2535,7 @@ copy_to_mode_reg (SImode, GEN_INT (-1)), GEN_INT (0x6))); emit_insn (gen_div_trap (operands[2], - copy_to_mode_reg (SImode, GEN_INT (0x80000000)), + copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } @@ -2575,7 +2575,7 @@ copy_to_mode_reg (DImode, GEN_INT (-1)), GEN_INT (0x6))); emit_insn (gen_div_trap (operands[2], - copy_to_mode_reg (DImode, GEN_INT (0x80000000)), + copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } @@ -2615,7 +2615,7 @@ copy_to_mode_reg (SImode, GEN_INT (-1)), GEN_INT (0x6))); emit_insn (gen_div_trap (operands[2], - copy_to_mode_reg (SImode, GEN_INT (0x80000000)), + copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } @@ -2655,7 +2655,7 @@ copy_to_mode_reg (DImode, GEN_INT (-1)), GEN_INT (0x6))); emit_insn (gen_div_trap (operands[2], - copy_to_mode_reg (DImode, GEN_INT (0x80000000)), + copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)), GEN_INT (0x6))); } @@ -4319,7 +4319,7 @@ move\\t%0,%z4\\n\\ emit_label (label1); emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); - emit_move_insn (reg3, GEN_INT (0x80000000)); + emit_move_insn (reg3, GEN_INT (BITMASK_HIGH)); emit_insn (gen_fix_truncdfsi2 (operands[0], reg2)); emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); @@ -4362,7 +4362,7 @@ move\\t%0,%z4\\n\\ emit_label (label1); emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1)); - emit_move_insn (reg3, GEN_INT (0x80000000)); + emit_move_insn (reg3, GEN_INT (BITMASK_HIGH)); emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); emit_insn (gen_fix_truncdfdi2 (operands[0], reg2)); @@ -4406,7 +4406,7 @@ move\\t%0,%z4\\n\\ emit_label (label1); emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); - emit_move_insn (reg3, GEN_INT (0x80000000)); + emit_move_insn (reg3, GEN_INT (BITMASK_HIGH)); emit_insn (gen_fix_truncsfsi2 (operands[0], reg2)); emit_insn (gen_iorsi3 (operands[0], operands[0], reg3)); @@ -4449,7 +4449,7 @@ move\\t%0,%z4\\n\\ emit_label (label1); emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1)); - emit_move_insn (reg3, GEN_INT (0x80000000)); + emit_move_insn (reg3, GEN_INT (BITMASK_HIGH)); emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32))); emit_insn (gen_fix_truncsfdi2 (operands[0], reg2)); @@ -5179,8 +5179,8 @@ move\\t%0,%z4\\n\\ (match_dup 3)))] " { - operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000); - operands[3] = GEN_INT (INTVAL (operands[1]) & 0x0000ffff); + operands[2] = GEN_INT (INTVAL (operands[1]) & BITMASK_UPPER16); + operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16); }") ;; Unlike most other insns, the move insns can't be split with -- 2.7.4