From 3a5a75b53a278188c21a2a2dc53ebf309a2b1a09 Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Wed, 26 Oct 2016 16:17:54 +0000 Subject: [PATCH] Adapt atomic compare and swap to ARMv8-M Baseline 2016-10-26 Thomas Preud'homme gcc/ * config/arm/sync.md (atomic_compare_and_swap_1): Add new ARMv8-M Baseline only alternatives to (i) hold store atomic success value in a return register rather than a scratch register, (ii) use a low register for it and to (iii) ensure the cbranchsi insn generated by the split respect the constraints of Thumb-1 cbranchsi4_insn and cbranchsi4_scratch. * config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate constraints must match those in atomic_compare_and_swap. (cbranchsi4_scratch): Likewise. From-SVN: r241578 --- gcc/ChangeLog | 12 ++++++++++++ gcc/config/arm/sync.md | 34 ++++++++++++++++++++-------------- gcc/config/arm/thumb1.md | 6 ++++++ 3 files changed, 38 insertions(+), 14 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5a79b96..12f9c02 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,17 @@ 2016-10-26 Thomas Preud'homme + * config/arm/sync.md (atomic_compare_and_swap_1): Add new ARMv8-M + Baseline only alternatives to (i) hold store atomic success value in a + return register rather than a scratch register, (ii) use a low register + for it and to (iii) ensure the cbranchsi insn generated by the split + respect the constraints of Thumb-1 cbranchsi4_insn and + cbranchsi4_scratch. + * config/arm/thumb1.md (cbranchsi4_insn): Add comment to indicate + constraints must match those in atomic_compare_and_swap. + (cbranchsi4_scratch): Likewise. + +2016-10-26 Thomas Preud'homme + * config/arm/arm.c (arm_expand_compare_and_swap): Add new bdst local variable. Add the new parameter to the insn generator. Set that parameter to be CC flag for 32-bit targets, bval otherwise. Set the diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index b4e0713..583b0af 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -189,21 +189,23 @@ DONE; }) +;; Constraints of this pattern must be at least as strict as those of the +;; cbranchsi operations in thumb1.md and aim to be as permissive. (define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c") ;; bool out + [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) - (set (match_operand:SI 1 "s_register_operand" "=&r") ;; val out + (set (match_operand:SI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out (zero_extend:SI - (match_operand:NARROW 2 "mem_noofs_operand" "+Ua"))) ;; memory + (match_operand:NARROW 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua"))) ;; memory (set (match_dup 2) (unspec_volatile:NARROW - [(match_operand:SI 3 "arm_add_operand" "rIL") ;; expected - (match_operand:NARROW 4 "s_register_operand" "r") ;; desired + [(match_operand:SI 3 "arm_add_operand" "rIL,lIL*h,J,*r") ;; expected + (match_operand:NARROW 4 "s_register_operand" "r,r,r,r") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f VUNSPEC_ATOMIC_CAS)) - (clobber (match_scratch:SI 8 "=&r"))] + (clobber (match_scratch:SI 8 "=&r,X,X,X"))] "" "#" "&& reload_completed" @@ -211,27 +213,30 @@ { arm_split_compare_and_swap (operands); DONE; - }) + } + [(set_attr "arch" "32,v8mb,v8mb,v8mb")]) (define_mode_attr cas_cmp_operand [(SI "arm_add_operand") (DI "cmpdi_operand")]) (define_mode_attr cas_cmp_str [(SI "rIL") (DI "rDi")]) +;; Constraints of this pattern must be at least as strict as those of the +;; cbranchsi operations in thumb1.md and aim to be as permissive. (define_insn_and_split "atomic_compare_and_swap_1" - [(set (match_operand 0 "cc_register_operand" "=&c") ;; bool out + [(set (match_operand 0 "cc_register_operand" "=&c,&l,&l,&l") ;; bool out (unspec_volatile:CC_Z [(const_int 0)] VUNSPEC_ATOMIC_CAS)) - (set (match_operand:SIDI 1 "s_register_operand" "=&r") ;; val out - (match_operand:SIDI 2 "mem_noofs_operand" "+Ua")) ;; memory + (set (match_operand:SIDI 1 "s_register_operand" "=&r,&l,&0,&l*h") ;; val out + (match_operand:SIDI 2 "mem_noofs_operand" "+Ua,Ua,Ua,Ua")) ;; memory (set (match_dup 2) (unspec_volatile:SIDI - [(match_operand:SIDI 3 "" "") ;; expect - (match_operand:SIDI 4 "s_register_operand" "r") ;; desired + [(match_operand:SIDI 3 "" ",lIL*h,J,*r") ;; expect + (match_operand:SIDI 4 "s_register_operand" "r,r,r,r") ;; desired (match_operand:SI 5 "const_int_operand") ;; is_weak (match_operand:SI 6 "const_int_operand") ;; mod_s (match_operand:SI 7 "const_int_operand")] ;; mod_f VUNSPEC_ATOMIC_CAS)) - (clobber (match_scratch:SI 8 "=&r"))] + (clobber (match_scratch:SI 8 "=&r,X,X,X"))] "" "#" "&& reload_completed" @@ -239,7 +244,8 @@ { arm_split_compare_and_swap (operands); DONE; - }) + } + [(set_attr "arch" "32,v8mb,v8mb,v8mb")]) (define_insn_and_split "atomic_exchange" [(set (match_operand:QHSD 0 "s_register_operand" "=&r") ;; output diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index cd98de7..67f2878 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1059,6 +1059,9 @@ (const_string "multiple")))] ) +;; Changes to the constraints of this pattern must be propagated to those of +;; atomic compare_and_swap splitters in sync.md. These must be at least as +;; strict as the constraints here and aim to be as permissive. (define_insn "cbranchsi4_insn" [(set (pc) (if_then_else (match_operator 0 "arm_comparison_operator" @@ -1120,6 +1123,9 @@ (set_attr "type" "multiple")] ) +;; Changes to the constraints of this pattern must be propagated to those of +;; atomic compare_and_swap splitters in sync.md. These must be at least as +;; strict as the constraints here and aim to be as permissive. (define_insn "cbranchsi4_scratch" [(set (pc) (if_then_else (match_operator 4 "arm_comparison_operator" -- 2.7.4