From 3a3f725a3cdc44cacb8f9847404a148ee056c913 Mon Sep 17 00:00:00 2001 From: Elena Lepilkina Date: Wed, 14 Dec 2022 18:37:44 +0300 Subject: [PATCH] [RISCV] Omit SRA in case of setlt or setge with zero constant Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D140206 --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 13 +++++++++++++ llvm/test/CodeGen/RISCV/branch_zero.ll | 2 -- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index a5f2092..7138273 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -9550,6 +9550,19 @@ static SDValue tryDemorganOfBooleanCondition(SDValue Cond, SelectionDAG &DAG) { static bool combine_CC(SDValue &LHS, SDValue &RHS, SDValue &CC, const SDLoc &DL, SelectionDAG &DAG, const RISCVSubtarget &Subtarget) { ISD::CondCode CCVal = cast(CC)->get(); + + // As far as arithmetic right shift always saves the sign, + // shift can be omitted. + // Fold setlt (sra X, N), 0 -> setlt X, 0 and + // setge (sra X, N), 0 -> setge X, 0 + if (auto *RHSConst = dyn_cast(RHS.getNode())) { + if ((CCVal == ISD::SETGE || CCVal == ISD::SETLT) && + LHS.getOpcode() == ISD::SRA && RHSConst->isZero()) { + LHS = LHS.getOperand(0); + return true; + } + } + if (!ISD::isIntEqualitySetCC(CCVal)) return false; diff --git a/llvm/test/CodeGen/RISCV/branch_zero.ll b/llvm/test/CodeGen/RISCV/branch_zero.ll index 2d6a3c9..fd09799 100644 --- a/llvm/test/CodeGen/RISCV/branch_zero.ll +++ b/llvm/test/CodeGen/RISCV/branch_zero.ll @@ -8,7 +8,6 @@ define void @foo(i16 %finder_idx) { ; CHECK-NEXT: .LBB0_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: slli a0, a0, 48 -; CHECK-NEXT: srai a0, a0, 48 ; CHECK-NEXT: bltz a0, .LBB0_4 ; CHECK-NEXT: # %bb.2: # %while.cond.preheader.i ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 @@ -50,7 +49,6 @@ define void @bar(i16 %finder_idx) { ; CHECK-NEXT: .LBB1_1: # %for.body ; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: slli a0, a0, 48 -; CHECK-NEXT: srai a0, a0, 48 ; CHECK-NEXT: bgez a0, .LBB1_4 ; CHECK-NEXT: # %bb.2: # %while.cond.preheader.i ; CHECK-NEXT: # in Loop: Header=BB1_1 Depth=1 -- 2.7.4