From 39f7488294bf2bbe6d9babd681bddcd854198239 Mon Sep 17 00:00:00 2001 From: Joey Gouly Date: Thu, 4 Jul 2013 10:04:08 +0000 Subject: [PATCH] Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision. llvm-svn: 185620 --- llvm/lib/Target/ARM/ARMInstrInfo.td | 2 + llvm/lib/Target/ARM/ARMInstrVFP.td | 56 +++++++++++++++++++++++++- llvm/test/MC/ARM/invalid-v8fp.s | 10 +++++ llvm/test/MC/ARM/v8fp.s | 23 +++++++++++ llvm/test/MC/Disassembler/ARM/invalid-v8fp.txt | 10 +++++ llvm/test/MC/Disassembler/ARM/v8fp.txt | 25 ++++++++++++ 6 files changed, 125 insertions(+), 1 deletion(-) create mode 100644 llvm/test/MC/ARM/invalid-v8fp.s create mode 100644 llvm/test/MC/ARM/v8fp.s create mode 100644 llvm/test/MC/Disassembler/ARM/invalid-v8fp.txt create mode 100644 llvm/test/MC/Disassembler/ARM/v8fp.txt diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 4d550ee..ed68b4e 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -203,6 +203,8 @@ def HasVFP3 : Predicate<"Subtarget->hasVFP3()">, AssemblerPredicate<"FeatureVFP3", "VFP3">; def HasVFP4 : Predicate<"Subtarget->hasVFP4()">, AssemblerPredicate<"FeatureVFP4", "VFP4">; +def HasV8FP : Predicate<"Subtarget->hasV8FP()">, + AssemblerPredicate<"FeatureV8FP", "V8FP">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate<"FeatureNEON", "NEON">; def HasFP16 : Predicate<"Subtarget->hasFP16()">, diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 597b74a..e1d470f 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -468,7 +468,7 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm, let Inst{4} = 0; } -// Between half-precision and single-precision. For disassembly only. +// Between half, single and double-precision. For disassembly only. // FIXME: Verify encoding after integrated assembler is working. def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm), @@ -493,6 +493,60 @@ def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm), /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm", [/* For disassembly only; pattern left blank */]>; +def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0, + (outs DPR:$Dd), (ins SPR:$Sm), + NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm", + []>, Requires<[HasV8FP]> { + // Instruction operands. + bits<5> Sm; + + // Encode instruction operands. + let Inst{3-0} = Sm{4-1}; + let Inst{5} = Sm{0}; +} + +def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0, + (outs SPR:$Sd), (ins DPR:$Dm), + NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm", + []>, Requires<[HasV8FP]> { + // Instruction operands. + bits<5> Sd; + bits<5> Dm; + + // Encode instruction operands. + let Inst{3-0} = Dm{3-0}; + let Inst{5} = Dm{4}; + let Inst{15-12} = Sd{4-1}; + let Inst{22} = Sd{0}; +} + +def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0, + (outs DPR:$Dd), (ins SPR:$Sm), + NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm", + []>, Requires<[HasV8FP]> { + // Instruction operands. + bits<5> Sm; + + // Encode instruction operands. + let Inst{3-0} = Sm{4-1}; + let Inst{5} = Sm{0}; +} + +def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0, + (outs SPR:$Sd), (ins DPR:$Dm), + NoItinerary, "vcvtt", ".f16.f64\t$Sd, $Dm", + []>, Requires<[HasV8FP]> { + // Instruction operands. + bits<5> Sd; + bits<5> Dm; + + // Encode instruction operands. + let Inst{15-12} = Sd{4-1}; + let Inst{22} = Sd{0}; + let Inst{3-0} = Dm{3-0}; + let Inst{5} = Dm{4}; +} + def VNEGD : ADuI<0b11101, 0b11, 0b0001, 0b01, 0, (outs DPR:$Dd), (ins DPR:$Dm), IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm", diff --git a/llvm/test/MC/ARM/invalid-v8fp.s b/llvm/test/MC/ARM/invalid-v8fp.s new file mode 100644 index 0000000..e2dbb8b --- /dev/null +++ b/llvm/test/MC/ARM/invalid-v8fp.s @@ -0,0 +1,10 @@ +@ RUN: llvm-mc -triple armv7 -show-encoding < %s | FileCheck %s + +@ VCVT{B,T} + + vcvtt.f64.f16 d3, s1 +@ CHECK-NOT: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee] + vcvtt.f16.f64 s5, d12 +@ CHECK-NOT: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee] + + diff --git a/llvm/test/MC/ARM/v8fp.s b/llvm/test/MC/ARM/v8fp.s new file mode 100644 index 0000000..f6bf7b9 --- /dev/null +++ b/llvm/test/MC/ARM/v8fp.s @@ -0,0 +1,23 @@ +@ RUN: llvm-mc -triple armv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s + +@ VCVT{B,T} + + vcvtt.f64.f16 d3, s1 +@ CHECK: vcvtt.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xee] + vcvtt.f16.f64 s5, d12 +@ CHECK: vcvtt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xee] + + vcvtb.f64.f16 d3, s1 +@ CHECK: vcvtb.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0xee] + vcvtb.f16.f64 s4, d1 +@ CHECK: vcvtb.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xee] + + vcvttge.f64.f16 d3, s1 +@ CHECK: vcvttge.f64.f16 d3, s1 @ encoding: [0xe0,0x3b,0xb2,0xae] + vcvttgt.f16.f64 s5, d12 +@ CHECK: vcvttgt.f16.f64 s5, d12 @ encoding: [0xcc,0x2b,0xf3,0xce] + + vcvtbeq.f64.f16 d3, s1 +@ CHECK: vcvtbeq.f64.f16 d3, s1 @ encoding: [0x60,0x3b,0xb2,0x0e] + vcvtblt.f16.f64 s4, d1 +@ CHECK: vcvtblt.f16.f64 s4, d1 @ encoding: [0x41,0x2b,0xb3,0xbe] diff --git a/llvm/test/MC/Disassembler/ARM/invalid-v8fp.txt b/llvm/test/MC/Disassembler/ARM/invalid-v8fp.txt new file mode 100644 index 0000000..dba48d8 --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/invalid-v8fp.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc -disassemble -triple armv7 -show-encoding < %s | FileCheck %s + +0xe0 0x3b 0xb2 0xee +# CHECK-NOT: vcvtt.f64.f16 d3, s1 + +0x41 0x2b 0xb3 0xee +# CHECK-NOT: vcvtb.f16.f64 s4, d1 + +0x41 0x2b 0xb3 0xbe +# CHECK-NOT: vcvtblt.f16.f64 s4, d1 diff --git a/llvm/test/MC/Disassembler/ARM/v8fp.txt b/llvm/test/MC/Disassembler/ARM/v8fp.txt new file mode 100644 index 0000000..76125da --- /dev/null +++ b/llvm/test/MC/Disassembler/ARM/v8fp.txt @@ -0,0 +1,25 @@ +# RUN: llvm-mc -disassemble -triple armv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s + +0xe0 0x3b 0xb2 0xee +# CHECK: vcvtt.f64.f16 d3, s1 + +0xcc 0x2b 0xf3 0xee +# CHECK: vcvtt.f16.f64 s5, d12 + +0x60 0x3b 0xb2 0xee +# CHECK: vcvtb.f64.f16 d3, s1 + +0x41 0x2b 0xb3 0xee +# CHECK: vcvtb.f16.f64 s4, d1 + +0xe0 0x3b 0xb2 0xae +# CHECK: vcvttge.f64.f16 d3, s1 + +0xcc 0x2b 0xf3 0xce +# CHECK: vcvttgt.f16.f64 s5, d12 + +0x60 0x3b 0xb2 0x0e +# CHECK: vcvtbeq.f64.f16 d3, s1 + +0x41 0x2b 0xb3 0xbe +# CHECK: vcvtblt.f16.f64 s4, d1 -- 2.7.4