From 39d2411c3bc30612fa873f11301ea954d774ff4e Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Wed, 16 Mar 2016 00:41:21 +0000 Subject: [PATCH] [X86] Regenerated widen load tests llvm-svn: 263608 --- llvm/test/CodeGen/X86/widen_load-2.ll | 221 +++++++++++++++++++--------------- 1 file changed, 127 insertions(+), 94 deletions(-) diff --git a/llvm/test/CodeGen/X86/widen_load-2.ll b/llvm/test/CodeGen/X86/widen_load-2.ll index fad1fa3..aa48f05 100644 --- a/llvm/test/CodeGen/X86/widen_load-2.ll +++ b/llvm/test/CodeGen/X86/widen_load-2.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse4.2 | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s ; Test based on pr5626 to load/store ; @@ -6,10 +7,13 @@ %i32vec3 = type <3 x i32> define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { ; CHECK-LABEL: add3i32: -; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: paddd (%{{.*}}), %[[R0]] -; CHECK-NEXT: pextrd $2, %[[R0]], 8(%{{.*}}) -; CHECK-NEXT: movq %[[R0]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movdqa (%rsi), %xmm0 +; CHECK-NEXT: paddd (%rdx), %xmm0 +; CHECK-NEXT: pextrd $2, %xmm0, 8(%rdi) +; CHECK-NEXT: movq %xmm0, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i32vec3, %i32vec3* %ap, align 16 %b = load %i32vec3, %i32vec3* %bp, align 16 %x = add %i32vec3 %a, %b @@ -19,13 +23,16 @@ define void @add3i32(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { ; CHECK-LABEL: add3i32_2: -; CHECK: movq (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: pinsrd $2, 8(%{{.*}}), %[[R0]] -; CHECK-NEXT: movq (%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: pinsrd $2, 8(%{{.*}}), %[[R1]] -; CHECK-NEXT: paddd %[[R0]], %[[R1]] -; CHECK-NEXT: pextrd $2, %[[R1]], 8(%{{.*}}) -; CHECK-NEXT: movq %[[R1]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: pinsrd $2, 8(%rsi), %xmm0 +; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero +; CHECK-NEXT: pinsrd $2, 8(%rdx), %xmm1 +; CHECK-NEXT: paddd %xmm0, %xmm1 +; CHECK-NEXT: pextrd $2, %xmm1, 8(%rdi) +; CHECK-NEXT: movq %xmm1, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i32vec3, %i32vec3* %ap, align 8 %b = load %i32vec3, %i32vec3* %bp, align 8 %x = add %i32vec3 %a, %b @@ -36,13 +43,16 @@ define void @add3i32_2(%i32vec3* sret %ret, %i32vec3* %ap, %i32vec3* %bp) { %i32vec7 = type <7 x i32> define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { ; CHECK-LABEL: add7i32: -; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: paddd (%{{.*}}), %[[R0]] -; CHECK-NEXT: paddd 16(%{{.*}}), %[[R1]] -; CHECK-NEXT: pextrd $2, %[[R1]], 24(%{{.*}}) -; CHECK-NEXT: movq %[[R1]], 16(%{{.*}}) -; CHECK-NEXT: movdqa %[[R0]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movdqa (%rsi), %xmm0 +; CHECK-NEXT: movdqa 16(%rsi), %xmm1 +; CHECK-NEXT: paddd (%rdx), %xmm0 +; CHECK-NEXT: paddd 16(%rdx), %xmm1 +; CHECK-NEXT: pextrd $2, %xmm1, 24(%rdi) +; CHECK-NEXT: movq %xmm1, 16(%rdi) +; CHECK-NEXT: movdqa %xmm0, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i32vec7, %i32vec7* %ap, align 16 %b = load %i32vec7, %i32vec7* %bp, align 16 %x = add %i32vec7 %a, %b @@ -53,15 +63,18 @@ define void @add7i32(%i32vec7* sret %ret, %i32vec7* %ap, %i32vec7* %bp) { %i32vec12 = type <12 x i32> define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { ; CHECK-LABEL: add12i32: -; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: movdqa 32(%{{.*}}), %[[R2:xmm[0-9]+]] -; CHECK-NEXT: paddd (%{{.*}}), %[[R0]] -; CHECK-NEXT: paddd 16(%{{.*}}), %[[R1]] -; CHECK-NEXT: paddd 32(%{{.*}}), %[[R2]] -; CHECK-NEXT: movdqa %[[R2]], 32(%{{.*}}) -; CHECK-NEXT: movdqa %[[R1]], 16(%{{.*}}) -; CHECK-NEXT: movdqa %[[R0]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movdqa (%rsi), %xmm0 +; CHECK-NEXT: movdqa 16(%rsi), %xmm1 +; CHECK-NEXT: movdqa 32(%rsi), %xmm2 +; CHECK-NEXT: paddd (%rdx), %xmm0 +; CHECK-NEXT: paddd 16(%rdx), %xmm1 +; CHECK-NEXT: paddd 32(%rdx), %xmm2 +; CHECK-NEXT: movdqa %xmm2, 32(%rdi) +; CHECK-NEXT: movdqa %xmm1, 16(%rdi) +; CHECK-NEXT: movdqa %xmm0, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i32vec12, %i32vec12* %ap, align 16 %b = load %i32vec12, %i32vec12* %bp, align 16 %x = add %i32vec12 %a, %b @@ -73,13 +86,16 @@ define void @add12i32(%i32vec12* sret %ret, %i32vec12* %ap, %i32vec12* %bp) { %i16vec3 = type <3 x i16> define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp) nounwind { ; CHECK-LABEL: add3i16: -; CHECK: pmovzxwd (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: pmovzxwd (%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: paddd %[[R0]], %[[R1]] -; CHECK-NEXT: pextrw $4, %[[R1]], 4(%{{.*}}) -; CHECK-NEXT: pshufb {{.*}}, %[[R1]] -; CHECK-NEXT: pmovzxdq %[[R1]], %[[R0]] -; CHECK-NEXT: movd %[[R0]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: pmovzxwd {{.*#+}} xmm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero +; CHECK-NEXT: pmovzxwd {{.*#+}} xmm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero +; CHECK-NEXT: paddd %xmm0, %xmm1 +; CHECK-NEXT: pextrw $4, %xmm1, 4(%rdi) +; CHECK-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15] +; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero +; CHECK-NEXT: movd %xmm0, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i16vec3, %i16vec3* %ap, align 16 %b = load %i16vec3, %i16vec3* %bp, align 16 %x = add %i16vec3 %a, %b @@ -90,10 +106,13 @@ define void @add3i16(%i16vec3* nocapture sret %ret, %i16vec3* %ap, %i16vec3* %bp %i16vec4 = type <4 x i16> define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp) nounwind { ; CHECK-LABEL: add4i16: -; CHECK: movq (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: movq (%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: paddw %[[R0]], %[[R1]] -; CHECK-NEXT: movq %[[R1]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero +; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero +; CHECK-NEXT: paddw %xmm0, %xmm1 +; CHECK-NEXT: movq %xmm1, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i16vec4, %i16vec4* %ap, align 16 %b = load %i16vec4, %i16vec4* %bp, align 16 %x = add %i16vec4 %a, %b @@ -104,12 +123,15 @@ define void @add4i16(%i16vec4* nocapture sret %ret, %i16vec4* %ap, %i16vec4* %bp %i16vec12 = type <12 x i16> define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %bp) nounwind { ; CHECK-LABEL: add12i16: -; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: paddw (%{{.*}}), %[[R0]] -; CHECK-NEXT: paddw 16(%{{.*}}), %[[R1]] -; CHECK-NEXT: movq %[[R1]], 16(%{{.*}}) -; CHECK-NEXT: movdqa %[[R0]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movdqa (%rsi), %xmm0 +; CHECK-NEXT: movdqa 16(%rsi), %xmm1 +; CHECK-NEXT: paddw (%rdx), %xmm0 +; CHECK-NEXT: paddw 16(%rdx), %xmm1 +; CHECK-NEXT: movq %xmm1, 16(%rdi) +; CHECK-NEXT: movdqa %xmm0, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i16vec12, %i16vec12* %ap, align 16 %b = load %i16vec12, %i16vec12* %bp, align 16 %x = add %i16vec12 %a, %b @@ -120,15 +142,18 @@ define void @add12i16(%i16vec12* nocapture sret %ret, %i16vec12* %ap, %i16vec12* %i16vec18 = type <18 x i16> define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %bp) nounwind { ; CHECK-LABEL: add18i16: -; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: movdqa 32(%{{.*}}), %[[R2:xmm[0-9]+]] -; CHECK-NEXT: paddw (%{{.*}}), %[[R0]] -; CHECK-NEXT: paddw 16(%{{.*}}), %[[R1]] -; CHECK-NEXT: paddw 32(%{{.*}}), %[[R2]] -; CHECK-NEXT: movd %[[R2]], 32(%{{.*}}) -; CHECK-NEXT: movdqa %[[R1]], 16(%{{.*}}) -; CHECK-NEXT: movdqa %[[R0]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movdqa (%rsi), %xmm0 +; CHECK-NEXT: movdqa 16(%rsi), %xmm1 +; CHECK-NEXT: movdqa 32(%rsi), %xmm2 +; CHECK-NEXT: paddw (%rdx), %xmm0 +; CHECK-NEXT: paddw 16(%rdx), %xmm1 +; CHECK-NEXT: paddw 32(%rdx), %xmm2 +; CHECK-NEXT: movd %xmm2, 32(%rdi) +; CHECK-NEXT: movdqa %xmm1, 16(%rdi) +; CHECK-NEXT: movdqa %xmm0, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i16vec18, %i16vec18* %ap, align 16 %b = load %i16vec18, %i16vec18* %bp, align 16 %x = add %i16vec18 %a, %b @@ -140,14 +165,17 @@ define void @add18i16(%i16vec18* nocapture sret %ret, %i16vec18* %ap, %i16vec18* %i8vec3 = type <3 x i8> define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) nounwind { ; CHECK-LABEL: add3i8: -; CHECK: pmovzxbd (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: pmovzxbd (%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: paddd %[[R0]], %[[R1]] -; CHECK-NEXT: pextrb $8, %[[R1]], 2(%{{.*}}) -; CHECK-NEXT: pshufb {{.*}}, %[[R1]] -; CHECK-NEXT: pmovzxwq %[[R1]], %[[R0]] -; CHECK-NEXT: movd %[[R0]], %e[[R2:[abcd]]]x -; CHECK-NEXT: movw %[[R2]]x, (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero +; CHECK-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero +; CHECK-NEXT: paddd %xmm0, %xmm1 +; CHECK-NEXT: pextrb $8, %xmm1, 2(%rdi) +; CHECK-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u] +; CHECK-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero +; CHECK-NEXT: movd %xmm0, %eax +; CHECK-NEXT: movw %ax, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i8vec3, %i8vec3* %ap, align 16 %b = load %i8vec3, %i8vec3* %bp, align 16 %x = add %i8vec3 %a, %b @@ -158,15 +186,18 @@ define void @add3i8(%i8vec3* nocapture sret %ret, %i8vec3* %ap, %i8vec3* %bp) no %i8vec31 = type <31 x i8> define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind { ; CHECK-LABEL: add31i8: -; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]] -; CHECK-NEXT: movdqa 16(%{{.*}}), %[[R1:xmm[0-9]+]] -; CHECK-NEXT: paddb (%{{.*}}), %[[R0]] -; CHECK-NEXT: paddb 16(%{{.*}}), %[[R1]] -; CHECK-NEXT: pextrb $14, %[[R1]], 30(%{{.*}}) -; CHECK-NEXT: pextrw $6, %[[R1]], 28(%{{.*}}) -; CHECK-NEXT: pextrd $2, %[[R1]], 24(%{{.*}}) -; CHECK-NEXT: movq %[[R1]], 16(%{{.*}}) -; CHECK-NEXT: movdqa %[[R0]], (%{{.*}}) +; CHECK: # BB#0: +; CHECK-NEXT: movdqa (%rsi), %xmm0 +; CHECK-NEXT: movdqa 16(%rsi), %xmm1 +; CHECK-NEXT: paddb (%rdx), %xmm0 +; CHECK-NEXT: paddb 16(%rdx), %xmm1 +; CHECK-NEXT: pextrb $14, %xmm1, 30(%rdi) +; CHECK-NEXT: pextrw $6, %xmm1, 28(%rdi) +; CHECK-NEXT: pextrd $2, %xmm1, 24(%rdi) +; CHECK-NEXT: movq %xmm1, 16(%rdi) +; CHECK-NEXT: movdqa %xmm0, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq %a = load %i8vec31, %i8vec31* %ap, align 16 %b = load %i8vec31, %i8vec31* %bp, align 16 %x = add %i8vec31 %a, %b @@ -178,29 +209,31 @@ define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp %i8vec3pack = type { <3 x i8>, i8 } define void @rot(%i8vec3pack* nocapture sret %result, %i8vec3pack* %X, %i8vec3pack* %rot) nounwind { ; CHECK-LABEL: rot: -; CHECK: movdqa {{.*}}, %[[CONSTANT0:xmm[0-9]+]] -; CHECK-NEXT: movdqa {{.*}}, %[[SHUFFLE_MASK:xmm[0-9]+]] -; CHECK-NEXT: pshufb %[[SHUFFLE_MASK]], %[[CONSTANT0]] -; CHECK-NEXT: pmovzxwq %[[CONSTANT0]], %[[CONSTANT0]] -; CHECK-NEXT: movd %[[CONSTANT0]], %e[[R0:[abcd]]]x -; CHECK-NEXT: movw %[[R0]]x, (%[[PTR0:.*]]) -; CHECK-NEXT: movb $-98, 2(%[[PTR0]]) -; CHECK-NEXT: movdqa {{.*}}, %[[CONSTANT1:xmm[0-9]+]] -; CHECK-NEXT: pshufb %[[SHUFFLE_MASK]], %[[CONSTANT1]] -; CHECK-NEXT: pmovzxwq %[[CONSTANT1]], %[[CONSTANT1]] -; CHECK-NEXT: movd %[[CONSTANT1]], %e[[R1:[abcd]]]x -; CHECK-NEXT: movw %[[R1]]x, (%[[PTR1:.*]]) -; CHECK-NEXT: movb $1, 2(%[[PTR1]]) -; CHECK-NEXT: pmovzxbd (%[[PTR0]]), %[[X0:xmm[0-9]+]] -; CHECK-NEXT: movdqa %[[X0]], %[[X1:xmm[0-9]+]] -; CHECK-NEXT: psrld $1, %[[X1]] -; CHECK-NEXT: pblendw $192, %[[X0]], %[[X1]] -; CHECK-NEXT: pextrb $8, %[[X1]], 2(%{{.*}}) -; CHECK-NEXT: pshufb %[[SHUFFLE_MASK]], %[[X1]] -; CHECK-NEXT: pmovzxwq %[[X1]], %[[X3:xmm[0-9]+]] -; CHECK-NEXT: movd %[[X3]], %e[[R0:[abcd]]]x -; CHECK-NEXT: movw %[[R0]]x, (%{{.*}}) - +; CHECK: # BB#0: # %entry +; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <158,158,158,u> +; CHECK-NEXT: movdqa {{.*#+}} xmm1 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u> +; CHECK-NEXT: pshufb %xmm1, %xmm0 +; CHECK-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; CHECK-NEXT: movd %xmm0, %eax +; CHECK-NEXT: movw %ax, (%rsi) +; CHECK-NEXT: movb $-98, 2(%rsi) +; CHECK-NEXT: movdqa {{.*#+}} xmm0 = <1,1,1,u> +; CHECK-NEXT: pshufb %xmm1, %xmm0 +; CHECK-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero +; CHECK-NEXT: movd %xmm0, %eax +; CHECK-NEXT: movw %ax, (%rdx) +; CHECK-NEXT: movb $1, 2(%rdx) +; CHECK-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero +; CHECK-NEXT: movdqa %xmm0, %xmm2 +; CHECK-NEXT: psrld $1, %xmm2 +; CHECK-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3,4,5],xmm0[6,7] +; CHECK-NEXT: pextrb $8, %xmm2, 2(%rdi) +; CHECK-NEXT: pshufb %xmm1, %xmm2 +; CHECK-NEXT: pmovzxwq {{.*#+}} xmm0 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero +; CHECK-NEXT: movd %xmm0, %eax +; CHECK-NEXT: movw %ax, (%rdi) +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: retq entry: %storetmp = bitcast %i8vec3pack* %X to <3 x i8>* store <3 x i8> , <3 x i8>* %storetmp -- 2.7.4