From 39c41169ba1998c11d486ef644b904d9f9c6fa02 Mon Sep 17 00:00:00 2001 From: Iago Toral Quiroga Date: Fri, 14 May 2021 12:03:35 +0200 Subject: [PATCH] broadcom/compiler: consider RT component size when lowering logic ops in Vulkan MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit In Vulkan we configure our integer RTs to clamp automatically, so with logic operations we need to be careful and avoid overflows by discarding any bits that won't fit in the RT component size. Fixes remaining CTS test failures in: dEQP-VK.pipeline.logic_op.* Reviewed-by: Alejandro Piñeiro Part-of: --- src/broadcom/compiler/v3d_nir_lower_logic_ops.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/broadcom/compiler/v3d_nir_lower_logic_ops.c b/src/broadcom/compiler/v3d_nir_lower_logic_ops.c index c5c30ab..11782c7 100644 --- a/src/broadcom/compiler/v3d_nir_lower_logic_ops.c +++ b/src/broadcom/compiler/v3d_nir_lower_logic_ops.c @@ -235,6 +235,22 @@ v3d_emit_logic_op_raw(struct v3d_compile *c, nir_builder *b, nir_ssa_def *dst = v3d_nir_get_swizzled_channel(b, dst_chans, fmt_swz[i]); op_res[i] = v3d_logicop(b, c->fs_key->logicop_func, src, dst); + + /* In Vulkan we configure our integer RTs to clamp, so we need + * to ignore result bits that don't fit in the destination RT + * component size. + */ + if (c->key->environment == V3D_ENVIRONMENT_VULKAN) { + uint32_t bits = + util_format_get_component_bits( + c->fs_key->color_fmt[rt].format, + UTIL_FORMAT_COLORSPACE_RGB, i); + if (bits > 0 && bits < 32) { + nir_ssa_def *mask = + nir_imm_int(b, (1u << bits) - 1); + op_res[i] = nir_iand(b, op_res[i], mask); + } + } } nir_ssa_def *r[4]; -- 2.7.4