From 3998a8e79761fa4bb67c14d9c7720a64423f4a99 Mon Sep 17 00:00:00 2001 From: RamNalamothu Date: Fri, 5 Mar 2021 13:55:43 +0530 Subject: [PATCH] [AMDGPU] Do not attempt sgpr spills to vgpr, when it is disabled This covers a path missed in https://reviews.llvm.org/D95768. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D98013 --- llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 2 +- llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp index 5b33a49..b5ef1d7 100644 --- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp @@ -365,7 +365,7 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) { } } - if (!TII->isSGPRSpill(MI)) + if (!TII->isSGPRSpill(MI) || !TRI->spillSGPRToVGPR()) continue; int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex(); diff --git a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll index f1731c8..8485129 100644 --- a/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll +++ b/llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll @@ -8,13 +8,19 @@ declare hidden void @external_void_func_void() #0 ; GCN-LABEL: {{^}}callee_with_stack_and_call: ; SPILL-TO-VGPR: buffer_store_dword v40, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill ; SPILL-TO-VGPR: v_writelane_b32 v40, s33, 2 +; SPILL-TO-VGPR: v_writelane_b32 v40, s30, 0 +; SPILL-TO-VGPR: v_writelane_b32 v40, s31, 1 ; NO-SPILL-TO-VGPR: v_mov_b32_e32 v0, s33 ; NO-SPILL-TO-VGPR: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill +; NO-SPILL-TO-VGPR: v_writelane_b32 v1, s30, 0 +; NO-SPILL-TO-VGPR: v_writelane_b32 v1, s31, 1 +; NO-SPILL-TO-VGPR: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill ; GCN: s_swappc_b64 s[30:31], s[4:5] ; SPILL-TO-VGPR: v_readlane_b32 s4, v40, 0 ; SPILL-TO-VGPR: v_readlane_b32 s5, v40, 1 +; NO-SPILL-TO-VGPR: buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; NO-SPILL-TO-VGPR: v_readlane_b32 s4, v1, 0 ; NO-SPILL-TO-VGPR: v_readlane_b32 s5, v1, 1 -- 2.7.4