From 395cd33ba850989209834a2e332d21b42168cfaf Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Tue, 25 Jul 2023 07:50:08 -0400 Subject: [PATCH] AMDGPU: Remove trailing whitespace from documentation --- llvm/docs/AMDGPUUsage.rst | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index d90c83f..0a7ae20 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -999,21 +999,21 @@ The AMDGPU backend implements the following LLVM IR intrinsics. marked with the :ref:`afn ` flag. llvm.amdgcn.wave.reduce.umin Performs an arithmetic unsigned min reduction on the unsigned values - provided by each lane in the wavefront. + provided by each lane in the wavefront. Intrinsic takes a hint for reduction strategy using second operand 0: Target default preference, 1: `Iterative strategy`, and - 2: `DPP`. + 2: `DPP`. If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is currently only implemented for i32. - llvm.amdgcn.wave.reduce.umax Performs an arithmetic unsigned max reduction on the unsigned values + llvm.amdgcn.wave.reduce.umax Performs an arithmetic unsigned max reduction on the unsigned values provided by each lane in the wavefront. Intrinsic takes a hint for reduction strategy using second operand 0: Target default preference, 1: `Iterative strategy`, and - 2: `DPP`. + 2: `DPP`. If target does not support the DPP operations (e.g. gfx6/7), reduction will be performed using default iterative strategy. Intrinsic is currently only implemented for i32. -- 2.7.4