From 3914bebe91f6b557e61d6d74117762f9043593e0 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 4 Jan 2021 10:54:42 +0000 Subject: [PATCH] [AMDGPU] Handle v_fmac_legacy_f32 in SIFoldOperands Convert it to v_fma_legacy_f32 if it is profitable to do so, just like other mac instructions that are converted to their mad equivalents. Differential Revision: https://reviews.llvm.org/D94010 --- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 2 ++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll | 24 ++++++---------------- 2 files changed, 8 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp index 6dc01c3..892dc1f 100644 --- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp +++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp @@ -140,6 +140,8 @@ static unsigned macToMad(unsigned Opc) { return AMDGPU::V_FMA_F32; case AMDGPU::V_FMAC_F16_e64: return AMDGPU::V_FMA_F16_gfx9; + case AMDGPU::V_FMAC_LEGACY_F32_e64: + return AMDGPU::V_FMA_LEGACY_F32; } return AMDGPU::INSTRUCTION_LIST_END; } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll index 8bfb81d..e641d12 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll @@ -70,16 +70,10 @@ define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, ; SDAG-NEXT: v_interp_p2_f32_e32 v3, v1, attr0.y ; SDAG-NEXT: s_and_b32 exec_lo, exec_lo, s16 ; SDAG-NEXT: s_waitcnt lgkmcnt(0) -; SDAG-NEXT: image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D -; SDAG-NEXT: v_mov_b32_e32 v4, -1.0 -; SDAG-NEXT: v_mov_b32_e32 v5, -1.0 +; SDAG-NEXT: image_sample v[0:3], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D ; SDAG-NEXT: s_waitcnt vmcnt(0) -; SDAG-NEXT: v_fmac_legacy_f32_e64 v4, v7, 2.0 -; SDAG-NEXT: v_fmac_legacy_f32_e64 v5, v8, 2.0 -; SDAG-NEXT: v_mov_b32_e32 v2, v9 -; SDAG-NEXT: v_mov_b32_e32 v3, v10 -; SDAG-NEXT: v_mov_b32_e32 v0, v4 -; SDAG-NEXT: v_mov_b32_e32 v1, v5 +; SDAG-NEXT: v_fma_legacy_f32 v0, v0, 2.0, -1.0 +; SDAG-NEXT: v_fma_legacy_f32 v1, v1, 2.0, -1.0 ; SDAG-NEXT: ; return to shader part epilog ; ; GISEL-LABEL: main: @@ -100,16 +94,10 @@ define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, ; GISEL-NEXT: v_interp_p2_f32_e32 v2, v1, attr0.x ; GISEL-NEXT: s_and_b32 exec_lo, exec_lo, s16 ; GISEL-NEXT: s_waitcnt lgkmcnt(0) -; GISEL-NEXT: image_sample v[7:10], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D -; GISEL-NEXT: v_mov_b32_e32 v4, -1.0 -; GISEL-NEXT: v_mov_b32_e32 v5, -1.0 +; GISEL-NEXT: image_sample v[0:3], v[2:3], s[8:15], s[0:3] dmask:0xf dim:SQ_RSRC_IMG_2D ; GISEL-NEXT: s_waitcnt vmcnt(0) -; GISEL-NEXT: v_fmac_legacy_f32_e64 v4, v7, 2.0 -; GISEL-NEXT: v_fmac_legacy_f32_e64 v5, v8, 2.0 -; GISEL-NEXT: v_mov_b32_e32 v2, v9 -; GISEL-NEXT: v_mov_b32_e32 v3, v10 -; GISEL-NEXT: v_mov_b32_e32 v0, v4 -; GISEL-NEXT: v_mov_b32_e32 v1, v5 +; GISEL-NEXT: v_fma_legacy_f32 v0, v0, 2.0, -1.0 +; GISEL-NEXT: v_fma_legacy_f32 v1, v1, 2.0, -1.0 ; GISEL-NEXT: ; return to shader part epilog %i = bitcast <2 x i32> %arg7 to <2 x float> %i22 = extractelement <2 x float> %i, i32 0 -- 2.7.4