From 3901dd3e4126d6349deb63686be99ac7fd7b94f6 Mon Sep 17 00:00:00 2001 From: Cullen Rhodes Date: Mon, 3 Jun 2019 10:42:02 +0000 Subject: [PATCH] [AArch64][SVE2] Add CPU and arch directive tests Summary: This patch adds tests for directives .arch, .arch_extension and .cpu for all features defined in Arm SVE2 architecture extension. Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62602 llvm-svn: 362378 --- .../test/MC/AArch64/SVE2/directive-arch-negative.s | 31 ++++++++++++++++++++++ llvm/test/MC/AArch64/SVE2/directive-arch.s | 21 +++++++++++++++ .../SVE2/directive-arch_extension-negative.s | 31 ++++++++++++++++++++++ .../MC/AArch64/SVE2/directive-arch_extension.s | 21 +++++++++++++++ llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s | 31 ++++++++++++++++++++++ llvm/test/MC/AArch64/SVE2/directive-cpu.s | 21 +++++++++++++++ 6 files changed, 156 insertions(+) create mode 100644 llvm/test/MC/AArch64/SVE2/directive-arch-negative.s create mode 100644 llvm/test/MC/AArch64/SVE2/directive-arch.s create mode 100644 llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s create mode 100644 llvm/test/MC/AArch64/SVE2/directive-arch_extension.s create mode 100644 llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s create mode 100644 llvm/test/MC/AArch64/SVE2/directive-cpu.s diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s new file mode 100644 index 0000000..4b2ba03 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s @@ -0,0 +1,31 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch armv8-a+sve2 +.arch armv8-a+nosve2 +tbx z0.b, z1.b, z2.b +// CHECK: error: instruction requires: sve2 +// CHECK-NEXT: tbx z0.b, z1.b, z2.b + +.arch armv8-a+sve2-aes +.arch armv8-a+nosve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: error: instruction requires: sve2-aes +// CHECK-NEXT: aesd z23.b, z23.b, z13.b + +.arch armv8-a+sve2-sm4 +.arch armv8-a+nosve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: error: instruction requires: sve2-sm4 +// CHECK-NEXT: sm4e z0.s, z0.s, z0.s + +.arch armv8-a+sve2-sha3 +.arch armv8-a+nosve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: error: instruction requires: sve2-sha3 +// CHECK-NEXT: rax1 z0.d, z0.d, z0.d + +.arch armv8-a+bitperm +.arch armv8-a+nobitperm +bgrp z21.s, z10.s, z21.s +// CHECK: error: instruction requires: bitperm +// CHECK-NEXT: bgrp z21.s, z10.s, z21.s diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch.s b/llvm/test/MC/AArch64/SVE2/directive-arch.s new file mode 100644 index 0000000..94ef647 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/directive-arch.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch armv8-a+sve2 +tbx z0.b, z1.b, z2.b +// CHECK: tbx z0.b, z1.b, z2.b + +.arch armv8-a+sve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: aesd z23.b, z23.b, z13.b + +.arch armv8-a+sve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: sm4e z0.s, z0.s, z0.s + +.arch armv8-a+sve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: rax1 z0.d, z0.d, z0.d + +.arch armv8-a+bitperm +bgrp z21.s, z10.s, z21.s +// CHECK: bgrp z21.s, z10.s, z21.s diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s new file mode 100644 index 0000000..5db80e1 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s @@ -0,0 +1,31 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch_extension sve2 +.arch_extension nosve2 +tbx z0.b, z1.b, z2.b +// CHECK: error: instruction requires: sve2 +// CHECK-NEXT: tbx z0.b, z1.b, z2.b + +.arch_extension sve2-aes +.arch_extension nosve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: error: instruction requires: sve2-aes +// CHECK-NEXT: aesd z23.b, z23.b, z13.b + +.arch_extension sve2-sm4 +.arch_extension nosve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: error: instruction requires: sve2-sm4 +// CHECK-NEXT: sm4e z0.s, z0.s, z0.s + +.arch_extension sve2-sha3 +.arch_extension nosve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: error: instruction requires: sve2-sha3 +// CHECK-NEXT: rax1 z0.d, z0.d, z0.d + +.arch_extension bitperm +.arch_extension nobitperm +bgrp z21.s, z10.s, z21.s +// CHECK: error: instruction requires: bitperm +// CHECK-NEXT: bgrp z21.s, z10.s, z21.s diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s new file mode 100644 index 0000000..257f572 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.arch_extension sve2 +tbx z0.b, z1.b, z2.b +// CHECK: tbx z0.b, z1.b, z2.b + +.arch_extension sve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: aesd z23.b, z23.b, z13.b + +.arch_extension sve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: sm4e z0.s, z0.s, z0.s + +.arch_extension sve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: rax1 z0.d, z0.d, z0.d + +.arch_extension bitperm +bgrp z21.s, z10.s, z21.s +// CHECK: bgrp z21.s, z10.s, z21.s diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s new file mode 100644 index 0000000..542a6f6 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s @@ -0,0 +1,31 @@ +// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.cpu generic+sve2 +.cpu generic+nosve2 +tbx z0.b, z1.b, z2.b +// CHECK: error: instruction requires: sve2 +// CHECK-NEXT: tbx z0.b, z1.b, z2.b + +.cpu generic+sve2-aes +.cpu generic+nosve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: error: instruction requires: sve2-aes +// CHECK-NEXT: aesd z23.b, z23.b, z13.b + +.cpu generic+sve2-sm4 +.cpu generic+nosve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: error: instruction requires: sve2-sm4 +// CHECK-NEXT: sm4e z0.s, z0.s, z0.s + +.cpu generic+sve2-sha3 +.cpu generic+nosve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: error: instruction requires: sve2-sha3 +// CHECK-NEXT: rax1 z0.d, z0.d, z0.d + +.cpu generic+bitperm +.cpu generic+nobitperm +bgrp z21.s, z10.s, z21.s +// CHECK: error: instruction requires: bitperm +// CHECK-NEXT: bgrp z21.s, z10.s, z21.s diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu.s b/llvm/test/MC/AArch64/SVE2/directive-cpu.s new file mode 100644 index 0000000..a8ca7b3 --- /dev/null +++ b/llvm/test/MC/AArch64/SVE2/directive-cpu.s @@ -0,0 +1,21 @@ +// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s + +.cpu generic+sve2 +tbx z0.b, z1.b, z2.b +// CHECK: tbx z0.b, z1.b, z2.b + +.cpu generic+sve2-aes +aesd z23.b, z23.b, z13.b +// CHECK: aesd z23.b, z23.b, z13.b + +.cpu generic+sve2-sm4 +sm4e z0.s, z0.s, z0.s +// CHECK: sm4e z0.s, z0.s, z0.s + +.cpu generic+sve2-sha3 +rax1 z0.d, z0.d, z0.d +// CHECK: rax1 z0.d, z0.d, z0.d + +.cpu generic+bitperm +bgrp z21.s, z10.s, z21.s +// CHECK: bgrp z21.s, z10.s, z21.s -- 2.7.4