From 38df949f98e7bdaccaa1bc1557e5cb68e52791df Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Mon, 15 Feb 2021 22:01:02 +0100 Subject: [PATCH] nir: Add tessellation related AMD-specific intrinsics. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Timur Kristóf Reviewed-by: Rhys Perry Part-of: --- src/compiler/nir/nir_divergence_analysis.c | 6 ++++++ src/compiler/nir/nir_intrinsics.py | 12 ++++++++++++ src/compiler/nir/nir_range_analysis.c | 5 +++++ 3 files changed, 23 insertions(+) diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 97c4f11..cceecfa 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -136,6 +136,11 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_line_width: case nir_intrinsic_load_aa_line_width: case nir_intrinsic_load_fb_layers_v3d: + case nir_intrinsic_load_tcs_num_patches_amd: + case nir_intrinsic_load_ring_tess_factors_amd: + case nir_intrinsic_load_ring_tess_offchip_amd: + case nir_intrinsic_load_ring_tess_factors_offset_amd: + case nir_intrinsic_load_ring_tess_offchip_offset_amd: is_divergent = false; break; @@ -473,6 +478,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_mbcnt_amd: case nir_intrinsic_elect: case nir_intrinsic_load_tlb_color_v3d: + case nir_intrinsic_load_tess_rel_patch_id_amd: is_divergent = true; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 8462956..aac932d 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1141,6 +1141,18 @@ intrinsic("load_buffer_amd", src_comp=[4, 1, 1], dest_comp=0, indices=[BASE, IS_ # src[] = { store value, descriptor, base address, scalar offset } intrinsic("store_buffer_amd", src_comp=[0, 4, 1, 1], indices=[BASE, WRITE_MASK, IS_SWIZZLED, SLC_AMD, MEMORY_MODES]) +# Descriptor where TCS outputs are stored for TES +system_value("ring_tess_offchip_amd", 4) +system_value("ring_tess_offchip_offset_amd", 1) +# Descriptor where TCS outputs are stored for the HW tessellator +system_value("ring_tess_factors_amd", 4) +system_value("ring_tess_factors_offset_amd", 1) + +# Number of patches processed by each TCS workgroup +system_value("tcs_num_patches_amd", 1) +# Relative tessellation patch ID within the current workgroup +system_value("tess_rel_patch_id_amd", 1) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel diff --git a/src/compiler/nir/nir_range_analysis.c b/src/compiler/nir/nir_range_analysis.c index f4ee069..bbee87a 100644 --- a/src/compiler/nir/nir_range_analysis.c +++ b/src/compiler/nir/nir_range_analysis.c @@ -1388,6 +1388,11 @@ nir_unsigned_upper_bound(nir_shader *shader, struct hash_table *range_ht, res = MAX2(src0, src1); break; } + case nir_intrinsic_load_tess_rel_patch_id_amd: + case nir_intrinsic_load_tcs_num_patches_amd: + /* Very generous maximum: TCS/TES executed by largest possible workgroup */ + res = config->max_work_group_invocations / MAX2(shader->info.tess.tcs_vertices_out, 1u); + break; default: break; } -- 2.7.4